I have been trying to model the practical functionality of a Regenerative comparator (latched comparator) to be used as a behavioral model in a pipeline ADC. I have searched for models with similar resemblance, but most of the models seem to be ideal comparators. I would greatly appreciate any help regarding this.
I tried to model using laplace_nd for the +ve and -ve resistance of the comparator, but somehow the model doesn't seem to work as it gets into a simulation convergence problem.
Also I am looking for documentation on Industry standard methodologies for developing Verilog-A models.
Thanks in Advance
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