Hi all,

I'm relatively new to Verilog-A and I am trying to write an entire library of logic components.  I have had much success, having models for almost every gate the IC designers I work with could ever want, but I am having trouble modeling Transmission Gates and Tristate inverters.  

As many of you well know a PPCLATCH is a type of Flip flop operating under a latch type operation.  An initial T-Gate first passes information to the first feedback loop.  Then at the change of the clock, the information is passed through a second, now open T-gate and is fed into a second feedback loop which maintains a voltage until a new voltage is passed through the second T-Gate again.  

I can model the PPCLATCH as a whole, as just a standard flip flop, my problems occur when I try using the schematic design with my Verilog-A models of T-Gates and Tristate inverters instead of the transistor models.

Again as you know T-Gates and Tristate inverters have a state where a certain combination of inputs can turn off the gate, meaning no current flows out of the gate and the output node is essentially floating.  I was modeling this state as having no change on the output voltage of the gate, because it seemed to me that the overall charge at the outputs would remain the same if the gate was off.  So I just had the transition function's first argument equal to the voltage it was already, the output voltage would transition to its same value, i.e. no change.  But as i found out, this leads to some really nasty problems when two outputs are both attached to the same node, like in the case of the PPCLATCH's T-GATE output and feed back loop.  With the Tristate inverter passing a low voltage even though it should be floating and the T-Gate passing a high voltage when its on, I have two verilog-A gates that both want to be in control of 1 node at the same time and neither will give in.  It leads to nasty convergence errors.  

My question is if there is a way to simulate a floating node based on the inputs.  I could model it as a switch but the input voltage is coming from another Verilog-A gate with infinite drive.  how high do I have to set the impedance of the open switch so that the output node is floating when the gates are off?  My attempts to simulate it as a switch are getting some weird results.

Anyway thanks for the help from anyone who can.

sky

Hi Sky,

Please do not get upset, the community would have been more than happy to help if got the knowledge, time, ... etc.
You were just unlucky this time I would say.

Anyway, that would be great if you could post your solution as well. This is very likely to interest someone in the future !

Cheers,
Riad.