Your Sampling Speed is too high.
Following are the problems you will face.
1.The biggest problem is the noise transfer function. The quantizer white noise will be quite high at the output. For first order SDM cutoff at your corner frequency for the NTF will be quite high. To lower this you ned very high gain OPAMP.

2.Second problem is you need an OPAMP with very high bandwidth(because your sampling rate is too high), which will be difficult to achieve.

3. Most probably you will be using a single bit quantizer, this will reflect the jitter noise.

4. the KT/C noises of your switch.

5. The buffer SNR Bottleneck

6. OPAMP noise.

7. Your OPAMP slew rate requirement would be very high.

8. Your hysteresis errors at the quantizer output.

9. DAC error.

10. Bandgap error

11. Most Importantly your Bandgap noise.

I would like to suggest you a feasibility study using systemc-ams and systemc.

Please let me know if you need further help.  

Keep posting,
Regards,
Sumit

thanks for your inputs, Sumit,

Do you know how to find the conversion time for a delta sigma converts?
for example, given a input Vin, how fast we can get the output for a 16bit delta sigma ADC if OSR and bandwidth of Vin(Fin) are known?

Hello Berti,
 Thanks for sharing your experience. My question is that did you
  design first order sigma delta modulator meeting SNR > 140 dB ?
  It would be amazing to see the topology. Can you please share ?
  I am eager to see the Monte Carlo results also. I never said that
  it is impossible. But I never designed first order SDM system.
  Well my experience is quite limited and I have only worked on it for
  last seven years in which I only addressed second order or higher.
  It was my mistake that I considered it as a discrete time modulator.

Hello YCM,
 Calculating conversion time is absolutely possible. My question is
 do you want t for the modulator only or for entire ADC ?
 Your transfer functions of various stages gives you estimate of
 of total delay and conversion time. Let me know how can I help
 you. It would be a pleasure of mine to assist you.

 For your Idle tone problem you may use dithering. Followings are the
 types which might interest you :
 1. Noise-Shaped Dithering
 2. Subtractive Dithering
 3. Dynamic Noise-Shaped Dithering
 4. Adaptive Bit Flipping Dithering

Best Regards,
Sumit

Hello YCM,
 Thanks for the interest. Well I am a system designer. I look into things
 more theoretically. We should account for each delays and calculate
 things exactly.
 Firstly we need to know where is the delay (clocked  
 delay) in your SDM ? . Mean are you using the delay in integrator
 or dac or in quantizer or in all. If you have delay in integrator
 ( H(z) = 1/z-1) then the total delay in SDM signal path is one. If it is
 both in Integ and quant then the delay is 2. If your
 Integ H(z) = z/z-1  and quant is clocked then total delay due to
 SDM is one. Clocked DAC does not contribute to the signal path
 delay of SDM, it only affects STF,NTF and Stability of system.

2. Second point is CIC (considering you will be using a CIC to
   gain some number of bits). Look at this well. For a SDM of Order
   K the order of CIC required is L = K + 1
   For first Order K = 1 and L = 2.
   For Second Order K = 2 and L = 3 .
   This means the CIC will have L number of integrators and L number
   of differentiators. Now look at differentiators carefully. Each
   differentiator is a symmetric  FIR filter. For a symmetric FIR filter of
   N coefficients the group delay is N/2. For a differentiator it will
   be 1/2. Half delay!!!!! and you will have to compensate that. In your
   case you have 2 differentiator stages, which will produce
   1/2 + 1/2 = 1 delay (in decimated data rate). But you have a
   previous delay of one (probably) from SDM, two more delays
   ( probably) from two integrators and 1 delay at the down sampler
   (probably), all in SDM sampling rate. So altogether 1 + 2 + 1 = 4
   delays and you will have to match that. You will have to match
   these delays to get 1 (for differentiator) + 1 (for this calc).
   The way you can do this is, say you down sample in first CIC
   stage by a rate N. Then to accomodate these 4 delays into CIC is
   put a delay stage of N-4 beore CIC(at SDM clock rate) to get 2
   clock cycle at the output of CIC(with downsampled rate). So you
   got rid of fractional delays and got integral delay at CIC output.
   
3. Continue this for next CIC stages.

4. Try to fit a Symmetric FIR(If you are interested in it at all) so that
   the group delay would N/2. And you know if you have a FIR, that
   poses the conversion delay bottle neck. Add all the delays (for
   each block) and you get the conversion cycle

What are the next stages. How you are planning them.
Please let me know how is your downsampling and filtering scheme

Best Regards,
Sumit

P.S. : Just Checked your second order SDADC part. Well in most of the cases it would be the FIR(If you have at all) group delay.
It is absolutely possible to gain 16 bit resolution with your spec.
If I understand this spec is for some low frequency sensor application.
If it is true then you will have something called chopping (which will be
more crucial that other things). Chopping imposes some limitations
on DSP of ADC.
Well for this spec OSR of 1024 is sufficient. in safer side 2*1024
would be more interesting. In that case I would suggest a SDM
clock of 2MHz if possible.

I would like to give answer of last question first.

The decimation is in digital domain and downsampling by power of two is more easy. Thats why OSR is given as power of two. It is also possible to
downsample by any ratio, but it complicates the decimation circuit by
introducing interpolators in them.

For first question. I must confess that I did not understand your question well. If you want to down sample by using a counter only then you have some other problem/ If i understand it well then you will accumulate (integrate) inputs for N number of samples and then
give out one sample. But integrator alone has some problem. It has a pole at z = 1. It means the circuit will be unstable at dc. To use this efficiently you need to compensate this pole. Thats why using a differentiator(which introduces a zero at dc and compensates the pole).
If your output sampling rate is 1kHz and SDM sampling clock is 1MHz any way
you will have to downsample by 1024, then why not using the advantage. Note you will have to select a SDM clock which after
dividing by 1024 produces 1 kHz outpu sampling rate, which is not accurately 1MHz

For your conversion delay question, it is very important to know
your decimation scheme to answer this question

Regards,
Sumit

This diagram is not detailed and very much symbolic. simply lesser
sampling rate registered output wont give you any meaningful output.

Let us consider that "register" block as CIC. Then if you dont even have
delay compensation for integrators of cic then you have approximately(this term is very important) 1 delay of CKN cycle.

by the way you need to enter detailed study analysis and you are
at a very initial stage . Everybody needs to start from somewhere.
It is very good that you want to clear your concept about everything.
I liked this

Regards,
Sumit

One cycle of CKN will be your delay