Hello YCM,
Thanks for the interest. Well I am a system designer. I look into things
more theoretically. We should account for each delays and calculate
things exactly.
Firstly we need to know where is the delay (clocked
delay) in your SDM ? . Mean are you using the delay in integrator
or dac or in quantizer or in all. If you have delay in integrator
( H(z) = 1/z-1) then the total delay in SDM signal path is one. If it is
both in Integ and quant then the delay is 2. If your
Integ H(z) = z/z-1 and quant is clocked then total delay due to
SDM is one. Clocked DAC does not contribute to the signal path
delay of SDM, it only affects STF,NTF and Stability of system.
2. Second point is CIC (considering you will be using a CIC to
gain some number of bits). Look at this well. For a SDM of Order
K the order of CIC required is L = K + 1
For first Order K = 1 and L = 2.
For Second Order K = 2 and L = 3 .
This means the CIC will have L number of integrators and L number
of differentiators. Now look at differentiators carefully. Each
differentiator is a symmetric FIR filter. For a symmetric FIR filter of
N coefficients the group delay is N/2. For a differentiator it will
be 1/2. Half delay!!!!! and you will have to compensate that. In your
case you have 2 differentiator stages, which will produce
1/2 + 1/2 = 1 delay (in decimated data rate). But you have a
previous delay of one (probably) from SDM, two more delays
( probably) from two integrators and 1 delay at the down sampler
(probably), all in SDM sampling rate. So altogether 1 + 2 + 1 = 4
delays and you will have to match that. You will have to match
these delays to get 1 (for differentiator) + 1 (for this calc).
The way you can do this is, say you down sample in first CIC
stage by a rate N. Then to accomodate these 4 delays into CIC is
put a delay stage of N-4 beore CIC(at SDM clock rate) to get 2
clock cycle at the output of CIC(with downsampled rate). So you
got rid of fractional delays and got integral delay at CIC output.
3. Continue this for next CIC stages.
4. Try to fit a Symmetric FIR(If you are interested in it at all) so that
the group delay would N/2. And you know if you have a FIR, that
poses the conversion delay bottle neck. Add all the delays (for
each block) and you get the conversion cycle
What are the next stages. How you are planning them.
Please let me know how is your downsampling and filtering scheme
Best Regards,
Sumit
P.S. : Just Checked your second order SDADC part. Well in most of the cases it would be the FIR(If you have at all) group delay.
It is absolutely possible to gain 16 bit resolution with your spec.
If I understand this spec is for some low frequency sensor application.
If it is true then you will have something called chopping (which will be
more crucial that other things). Chopping imposes some limitations
on DSP of ADC.
Well for this spec OSR of 1024 is sufficient. in safer side 2*1024
would be more interesting. In that case I would suggest a SDM
clock of 2MHz if possible.