Hi YCM,
Please find my replies inline.
Hi Sumit,
I am going to use Matlab to run some simulations first.
>> Judicious. Use Matlab to find out the frequency response of entire
signal chain. Also analyze pole-zero plot for your SDM and settling
time for each block and entire signal chain. Optimize you SDM
topology by choosing proper coefficients.
By the way, if I use a second order single bit modulator followed for a sinc3 filter, (fin bandwidth=1kHz, OSR=1024, 16bit resolution) what is the total conversion time for the ADC? my understanding here is sinc3 filter needs N taps and N must be equal to OSR, so the delay of the filter is OSR which is equal to OSR*Tclk=Tinputsignal/2=1ms/2=0.5ms, is that correct? if that is correct, does not that mean the conversion time is always equal to half of the 1/fin without any relations with 16 bit resolution?
>> Well there are two things here. First is the group delay.
I your case it will be 3/2 cycle of downsampled clock(third order
CIC). It means 1ms*3/2 = 1.5 ms (at the output of CIC). The
answer changes if you have chopping/dechopping. In that case
CIC schemes will be different. Important to know about chopping.
I wont like non-integral delays anyway. I would have been
compensated it for 2 delays (not 3/2 delays).
Second is settling time. Means if suddenly input changes (say
from 0 to full scale, step input). Do a step response analysis in
Matlab on CIC or entire filter chain.
Please do a Monte Carlo Simulation on Matlab over pole zero and
frequency response to see the stability of your system.
Your integrator response will be somehow as follows :
H(z) = beta*z^-1/(1 - alpha*z^-1)
where beta = Cs/Cf
and alpha = 1.0 - beta/Aol (Aol = open loop gain of OPAMP)
beta is the gain of integrator and alpha is leakage.
vary Cs and Cf with a normal random number and plot response
and pole-zero plot of entire SDM. This will tell you about pole
spread and system response (by this term I mean both STF and
NTF), which in terns helps you determine the sizes of Cs and Cf
1ms *
also, how to explain the output of sinc3 filter? say if the inputs to ADC are 1/2, 1/4, 1/8 of full scale and ADC is 16 bit, sinc3 filter outputs are y(1), y(2), y(3) ...., how to explain y(1), y(2), y(3) ....? my understanding y(1)='00FF'H, y(2)='000F'H, y(3)='0003'H, is that correct?
>>> You know the answer partially. The answer is hidden in DNL and
INL requirements of an ADC. at zero input output has to be
0 and at full scale it would be 65535 (if you use unsigned
arithmetic, Note this is very important to select the arithmetic of
DSP. It helps reducing your current consumption. Example
signed arithmetic is good for upto 8 bits of registered width,
but for you it would be unsigned 2's complement as your bitwidth
will be 16 or more bits. Please refer Anantha Chandrakashan
for better understanding,
http://www-mtl.mit.edu/~anantha/publications.html).
Accordingly common mode(1/2) will be
32768. There is an issue here. You need to check your CIC gain
here. For example if you use CIC of DSR 64, the output gain
(D.C) will be around 108.37 dB. So you can achieve with 16 bits
output as 108.37 - 2*6 = 96.37 dB, which wont be 16 bits. This
is intrinsic characteristic of CIC. One example to fix this is
calibration coefficients.
If you are using a straight FIR implementation then for sinc3
filter u need N coefficients. That same filter can be reduced to
a CIC response, there u need 6 taps only
.
for 1024 down sample 1024 tap FIR is simply too large to
implement. So better to use its CIC reduced form
Thanks a lot
>>> You are always welcome
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