Just checked with my models. It should work with 3.3 volts supply.
what is ur supply voltage ?

BTW, Do u have a droop correction ?

Hello YCM,
 Sorry for the delayed response. I was busy with reviewing some designs.
After receiving this mail from you , I think you don't have any spec with you. I would like to know the application. 1.8 Volts gives me a feeling that
you want to design for audio application. Am I correct ?. This sounds like a student project.

Droop compensation comes when you want a clean frequency response of the system designed by you. The CIC introduces a droop at and around
band edge of the frequency response of your system. That can be corrected a FIR filter. Generally  a droop correction  FIR filter has high number
of coefficients (20 or higher). So obviously you will be having more conversion delay as FIR is generally last stage and operates at the lowest
sampling in your DSP. The use of such an FIR is also  desired to improve your stop-band attenuation (as CIC dosent have a very good stop-band
attenuation).

If you want to get rid of your common mode noise then it must be implemented as fully differential circuit. However, you can analyze your system
as single ended. Fully differential in system level doesn't have much impact.

Well chopper wont be there in sigma delta ADC. It will be at the input of your system, even before your buffer/PGA. It can be implemented using
a pair of switches. You need to find out your chopping frequency/rate, this depends on your output bandwidth/sampling rate. Depending on that
you will have to plan the bandwidth of each blocks in your system. Typically people obeys a thumb rule  as any block  after chopper will have a bandwidth
of 10-15 times the chopping frequency. I maintain it 20 times. The chopper frequency has to be at least 2 times your output sampling rate (downsampled
rate). Some people keeps it as their output sampling. Chopping is kind of a modulation and demodulation technique with the synchronization in mind (
delay matching in DSP). Your DSP needs to dechop the signal. The plan for such chopping/dechopping technique requires a seperate plan for your dsp.
The CIC needs to be divided into at least two parts and the dechopping needs to be done after first CIC. The selection of first CIC is critical. It needs
to have a lower DSR (it means fast settling time) to accommodate chop clock. By chopping you force the dc and 1/f noise to be thrown out to the
chopper frequency and this dc/(1/f) will be removed by the second CIC. Implementation of Chopper/dechopper requires some relaxed conversion rate
and your plan from sigma path needs to be well reviewed.

BR,
Sumit