Hi Folks,

I am trying to learn physical design and I have some basic questions that I'm hoping I could get some information on.

My entire tool flow is Synopsys. I have a MIPS32 processor in Verilog. I have synthesized into into a mapped netlist and done verification on it. It is all working. Now I'm ready to move onto automatic place/route, clock tree synthesis, power network synthesis, etc.

I have not done any floorplanning since I only have one big block which contains the entire mips32 core. I have an educational 90nm technology library which provides cells and I/O pads. I also have some reference scripts as a starting point to do begin physical design. I'm using IC Compiler for place/route.

One problem I have is understand pads vs pins. If my understanding is correct, do pins refer to the port at the block level? And the pads are pins at the top-level?

If that is the case and I only have one block which is the entire core, and I want the signals of this block are going out of the "chip", I would need to give the tool a pad constraint file to tell it where to locate the pads?

However, if I were doing floorplanning I would give a pin constraint file to let the tool know where put the pins on the edge of block?

Also how many pads on the chip boundary should be left for VDD/VSS? Is a pair on each side (so a total of 4 VDD and 4 VSS) sufficient or too much?

Also in my library there are pads classified as Digital , Analog, I/O, and VDD/GND. What is the difference between a Digital/Analog vs I/O pad?
Let's assume all the pins of the core are going to a cache (assume its located off chip). Should I just be using I/O pads? or Should Digital pads be used?

Thank you for any information to these newbie questions.