Hello,

There is no simple method, but the simplest method would depend on:

1. Type of ADC and its exact realization.
2. The level of your understanding of your ADC.
3. The amount of simulation time you want to spend.
4. Whether you want to know just the maximum INL/DNL or INL/DNL for all codes/levels.

Let me give an example:

If you have a conventional SAR ADC with a comparator, then you know that the worst-case DNL will occur at the halfway mark. Depending on your level of understanding of the various nonidealities, you would then probably minimize one or more (say in this case, nonidealities due to finite settling time of switches, comparator etc.), leaving only the capacitor mismatch. Likewise, you know that worst-case INL usually occurs out-of-phase with worst-case DNL. This is partially true when the INL is due to mismatch only (INL and DNL correlated). This is not true of course if your INL is coming from sampling switch nonidealities or gain compression in the opamp. But you get the idea.

You could theoretically simply build a MATLAB or a pen-paper model
and work out the worst-case INL/DNL. This would be quite fast.

Or you could run Monte Carlo sims on the whole transistor-level ADC concentrating on the region around the halfway level.

I recommend using a combination of methods. It seems to me that you are asking for these tips a little late in your design cycle (your ADC is ready in schematic). The better method would have been to have decided before starting the design how you were going to tackle this problem. What I normally do:

1. Look at various architectures to see which one has what advantages/disadvantages.

2. See which of these I can fit best to my spec with reasonable effort/cost/power consumption.

3. Built a model in MATLAB (or C) to cover the major nonidealities.

4. Make a high-level design and a budget for the various errors. Based on this, you will specify things like settling time of the switches, comparators, opamps etc., the amount of error due to mismatch. This budget is made for each step/stage used in your ADC.

5. From the above, you can identify critical "crossover points" and focus only on these while running transistor-level simulations.

6. Simulate stages of the ADC separately at transistor-level to see if the specs are met for the individual stages. This must be done at the worst-case corners (again you must know which ones these will be for your design).

7. If you really want, you could then run some simulations of the entire ADC at top level. This is rather time-intensive. I recommend that you identify some worst-cases with a MATLAB sim first, and introduce the corresponding nonideality (mismatch etc.) in the transistor-level model and then run a sim.

Best regards,

Vivek