Hi Yawei,

Depending on the speed and your signal generator, you might want to consider using a ramp signal instead of a sinewave. The number of samples needed drops dramatically since the distribution of the input codes is now uniform instead of bathtub. I remember using such a method for a 14b ADC. Already at 14b level, the number of samples needed was impractically high with a sinewave.

Naturally, there are several disadvantages, the most important being:

(a) difficulty in generating pure ramps.
(b) cannot use a filter to purify the signal.

What you can do in addition is to use a collection of tests to deduce the INL/DNL. In addition to the ramp test, I would recommend the following:

1. A fullpower sinewave test and FFT with coherent sampling (prime number of input cycles) in order to catch as many codes as possible.

2. Running several "localized" INL/DNL histogram tests with sinewave signals approx. FS/32 centered around various critical points in your code range. So for instance, if you had a traditional SAR ADC, you would run a histogram test around 0, +/- FS/2, etc.

3. Transferring data offline to a PC for INL/DNL analysis instead of using a logic analyzer. This may not work if you want to do rapid tests for INL/DNL (I doubt if anyone does that in production for 16b ADCs).

Regards,

Vivek