Hi All,
I have a layout of a circuit with standard cells and a schematic which is an imported verilog netlist. My standard cell library is not a complete library(MOSIS ARM standard cells) and it has a cmos_schematic with input out put pins for black box netlisting and supply and ground pins are not in the schematic. When I run LVS with black box option, it gives error, because it finds pin VSS and VDD and one more thing which I guess is substrate in the layout for each cell but it can not find those pins in schematic of the cells. Can any one tell me how to tell LVS in Assura that those VDD and VSS pins are connected inherently?


P.S. I read the Assura user guide but I couldn't understand how to define inherent pins.