It depends. There are some parts which are to do with device extraction - these are for characterized devices - maybe your poly resistor is not a "parasitic" device, in which case the extract rules can extract whatever physical parameters it likes, and then use those to model the device. This device extraction is part of the Assura LVS step.

For parasitic extraction, Assura RCX (which is now a tool called QRC, because it can be used with various LVS tools, not just Assura), will extract resistance, capacitance, inductance and mutual inductance (depending on your choices) for interconnect. The interconnect is generally what is left behind after the devices have been recognized and extracted by the LVS tool's extractor.

Regards,

Andrew.

MarcoC wrote on Sep 7^th, 2009, 5:51am:


As far as I know, if a parasitic extractor recognizes (through a prior LVS step) a structure as a "device" (that is supposed to be described by a compact model), then all capacitances and resistances within teh "device" are supposed to be described by the "device model", and capacitive/inductive coupling to the "outside world" is simply neglected.

In general, separating parasitics into"device" and "interconnects" may be vague and unphysical, especially in dense layouts. As an example, a poly-to-source/drain capacitance in a MOSFET (overlap capacitance) is captured by Spice device models. However, when contacts between diffusion and M1 are introduced, a significant fraction of overlap capacitance will be "redistributed" into poly-to-contact capacitance. Poly-to-contact capacitance may be difficult to include into Spice models as there is practically infinite number of possible arrangements (poly/contacts/diffusion), but accurate calculation of this capacitance in parasitic extraction would require the use of a field solver, while most of the field solvers are incapable to handle large layouts. Pattern-matching-based parasitic extractors can produce a very large error for complicated 3D structures that are typical in advanced technology nodes.

In general, compact models of the devices and parasitic extraction tools should "talk" to each other (i.e. agree on what capacitance component is included into device model or into parasitic extraction) - to avoid capacitance double-counting or "zero-counting". Even then, there is a gray area in device versus parasitic separation.