sheldon
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Vinay,
I agree with Raj, your question is hard to understand. Some things to consider with flash ADCs 1) Adding a bit doubles complexity 2) Adding a bit doubles power 3) Adding a bit doubles the load the input buffer has to drive --> In addition, to flash ADC having high non-linear input cap 4) Adding a bit requires improving the matching by a factor of two. Practically, the yield for a 12 bit ADC would be very low.
--> Most literature puts the limit of matching at 10 bits, 1 part in 1000 for device characteristics that match well, for example, resistance
5) I have not worked through the numbers, but settling of the reference voltage would also be a big challenge.
--> The reference resistor/input comparator is a highly non-linear transmission line. As the number of comparators increases settling time increases. The reference resistor can be tapped but then accurate tap voltages need to be generated.
6) The clock generator needs to trigger all the comparators at the same time or accuracy is degraded. The physically larger the ADC the more difficult this is to do.
There techniques to reduce the impact of these effects. However, the better solution is to adopt an architecture more suited for the application. Building a 12 bit flash ADC really is not even an interesting science experiment. It would be slow, hard to use, consume large amounts of power, ...
Best Regards,
Sheldon
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