Hi,
I want to design a comparator which is supposed to work up-to 1.5GHz. At that frequency how should I model the pin and outside world parasitic so that the design will work in the test board where I will be connecting the output pin through an IO cell(given by foundry) and then bond-pad and then some PCB trace of length around 4mm.At present I am using the parasitic extracted blocks of the comparator, the output driver, the IO cell and the bond pad parasitic for simulation. But my doubt is how should I consider the PCB trace parasitic and if I want to use the PCB trace to connect to the scope having 10pf load then how should I model the parasitic load in that case. For the input signal I am using an input buffer after the IO cell. I am also taking the schematic for the IO cell and also the bond-pad cap. for simulation. But what else should I put in my schematic to closely match the real life situation?
Thanks,
-pkd

as well as modelling everything on chip including the interconnect (which you seem to have fairly well covered), you'll then need the bondwire and package model. the exact model depends on the bonding and package you are using.
the package pin then contacts the pcb, so you'll get extra capacitance from that pcb pad as well. to model this you'll need to know the dimensions and layers of the pcb.
the 4mm pcb trace can simply be modelled as a microstrip line once you have all the pcb details.
given you'll have a scope probe on this output, the parasitic presented by the 4mm pcb trace should be relatively small compared to 10pF. also remember also the scope probe impedance, not just the capacitance.

hope this helps... cheers

aw

In addition to the advice you received so far, I suggest that you may also want to model the power distribution impedance on PCB/package/chip since it is part of the return current of your signal path transmission line.   Impedance discontinuities on the return path show on the input and output signals.

Cosmin Iorga, Ph.D.
NoiseCoupling.com
http://www.noisecoupling.com