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Vladislav D

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The LOD feature within a kit
Nov 04^th, 2009, 10:11pm

Hello colleagues,
I am using the models of transistors with LOD effect, however I am worried about if the shared dummies are placed, the influence of STI stress will be different �from I simulated. Of course, I can off LOD effect distance calculation but I am also not sure if this is good idea or not. I would be really appreciate any advice. What is tour experience? Thank you.

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Mayank

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Re: The LOD feature within a kit
Reply #1 - Nov 4^th, 2009, 10:38pm

Hello Vladislav,
I think my friend you are talking about the Shallow Trench Isolation Effect (fashionably abbreviated as STI or LOD effect...). I would suggest you to use multipliers instead of fingers to achieve better matching as far as STI is concerned...Inter-digited / common centroid layouts provide better matching and lesser STI mismatches...
As far as Layout is concerned, if you take care to place duimmies , you need not worry about STI at schematic level...It's a good practice to take layout effects into accout in schematic itself, but critical matching requires PLS iterations....In a critical matching requirement, go for common centroid with dummies and ensure the WPE/STI parameters in PLS netlist provide match....

Maybe, this document could help you further ---> www.ieee-cicc.org/06-8-6.pdf

regards,
Mayank.

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Vladislav D

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Re: The LOD feature within a kit
Reply #2 - Nov 5^th, 2009, 12:43am

Thank you for the answer. That article you mentioned is really good. Exactly the one became the source of my doubts

. However, I did not get it clearly. Let�s take an example, look in the picture. I have a transistor with two shared dummies. In schematic I did the simulation, spectre included LOD effect = 771nm but in reality this number will be less because of dummies that increase Sa ans Sb lengths. Of course, I can do PLS but my task to get the appropriate results in a circuit level.

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Mayank

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Re: The LOD feature within a kit
Reply #3 - Nov 5^th, 2009, 1:04am

Hello Vladislav,
Well there's only one way i can suggest...depending on the length and width of your MOS....Instead of the complete layout, draw a dummy layout of only that critical MOSFET without any fingers etc...Do two iterations, one with a dummy placed in layout...one without...Also change length and width of the dummy and do another iteration...This might be a one time thing....Check for changes in sa,sb,sc values..This might give you an estimate of sa,sb variation along with dummy length/width...

Then you can set sa,sb at schematic level, depending on whether your pdk allows you to do that or not...or change it in spectre netlist for critical MOSFETs...
From my experience, i would suggest you to take care of sa,sb values in PLS only....take precautions in layout to shield it against STI/WPE effects rather than compensating for them....

Maybe this article could put my point better :-- http://www.eetasia.com/ART_8800451526_499485_NT_288b3dee.HTM

--Mayank.

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