Hello Vladislav,
Well there's only one way i can suggest...depending on the length and width of your MOS....Instead of the complete layout, draw a dummy layout of only that critical MOSFET without any fingers etc...Do two iterations, one with a dummy placed in layout...one without...Also change length and width of the dummy and do another iteration...This might be a one time thing....Check for changes in sa,sb,sc values..This might give you an estimate of sa,sb variation along with dummy length/width...
Then you can set sa,sb at schematic level, depending on whether your pdk allows you to do that or not...or change it in spectre netlist for critical MOSFETs...
From my experience, i would suggest you to take care of sa,sb values in PLS only....take precautions in layout to shield it against STI/WPE effects rather than compensating for them....
Maybe this article could put my point better :--
http://www.eetasia.com/ART_8800451526_499485_NT_288b3dee.HTM--Mayank.