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Control logic circuitry for a SRAM-based register file (Read 3668 times)
pgbackup
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Control logic circuitry for a SRAM-based register file
Nov 09th, 2009, 9:25pm
 
Hi,

I'm trying to design a very simple SRAM-based register file that allows for 2 reads/1 write every clock cycle. There are 16 registers each w/ 8 bit. I have the basic SRAM cell, precharge circuitry, decoder, column mux, sense amplifiers, and i/o buffers working fine separately. I have verified them through SPICE simulations. The problem I'm encountering is the control logic circuitry to do the proper sequencing. I want to fabricate this test circuit on a 0.5 um technology and am targeting an read/write operation within 10 ns (100 Mhz processor clk).

I want to do the read on the positive edge of the clock and write on the falling edge. Finally, a precharge is done to get ready for the next operation in the next cycle.

For a read, I must first send a word_enable pulse to the decoder to assert the word line. The column circuitry is already enabled at the same time. Then a little bit later, I must send a pulse (phis) to enable the sense amplifier to read the data and output the full logic values. After that, when the system clock is ready to fall I enable the input buffer to drive the data onto the bit/bit bar lines. And then if write enable is asserted, I send a pulse to the write decoder to assert the word line for write. Finally, I must set phip=0 to being the precharge and get ready for the next read cycle.

My question is how do I go about implementing this control? The problem is this timing chain. I'm not sure how to send pulses. Since the processor clock only goes high for half the time and then low, how do I sequence all these steps? For example, the sense amplifier enable pulse has to be sent after the pulse to enable the world line has been sent. If it were a multi-cycle operation I could create a finite state machine, but that doesn't seem feasible here.

I would appreciate any ideas or things I can try out. Thank you for your time.
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AnalogDE
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Re: Control logic circuitry for a SRAM-based register file
Reply #1 - Nov 10th, 2009, 9:53am
 
You basically need to create pulses with delay chains...  I think any good SRAM book would have coverage of that.
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pgbackup
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Re: Control logic circuitry for a SRAM-based register file
Reply #2 - Dec 2nd, 2009, 10:23pm
 
Hi,

Thanks for your response. I was able to figure this out. Was flipping through the Weste's CMOS book and came across clock/delayed clocks/pulses. That was sufficient to get this simple design done. It works quite nicely.

Kind regards.
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