Pilo,

  Could you provide any other details, for example, the how are the switches modeled? What is the switch on-resistance?

                                                                   Best Regards,

                                                                      Sheldon

Pilo,

  Since the op-amps are ideal, they probably are not causing the
problem:

1) Are the capacitors linear capacitors or are they device capacitors?
   If the device capacitors are model as non-linear devices, then the
   you might try replacing them with linear capacitors. If the distortion
   improves, then the issue is the device capacitor non-linearity.

2) Switch test 1:
   You might try replacing the capacitors with the switch from bmslib.
   sw_no. This will allow you to see if the issues is the switches. If
   the distortion improves then the issue maybe that the switch on-
   resistance needs to be more linear across the voltage level.

3) Switch test 2:
   Use  the bmslib switches and lower the on-resistance, if the
   distortion improves, then there maybe a settling issue, the
   switch R X Capacitor RC time constant is too long for the
   time allowed to settle. Or incomplete settling is the source
   of the distortion.

4) You might also want to verify your assumption that the op-amps
   are ideal. If the op-amp models are not ideal then there are other
   issues that need to be explored.

5) BTW, you have not provided much detail so my assumption is that
   you are designing an audio SD expecting ~90-96 dB of SINAD
   are seeing ~70-80dB due to large distortion tones. That is basically
   you are close to your expected results with more distortion than
   expected. In addition, the other assumption is that structure is fully
   balanced, timing is correct, and the op-amps have high CMRR so
   that the effect of charge injection, ... can be neglected.

    This is nice place to use behavioral modeling to help you
    isolate the issue.

                                                                  Best Regards,

                                                                     Sheldon

I would recommend you to first do some additional reading (such as Design of Multi-Bit Delta-Sigma A/D Converters from Geerts, Steyaert and Sansen) to get a complete overview of non-idealities in the circuit. From this you should derive the circuit block specifications. Otherwise I might be difficult to achieve 18bits of resolution by just trusting the simulator...

Cheers

since your switches are at transistor level, don't underestimate their non linearities. A low on resistance is not enough, if the resistance changes with the signal amplitude it will increase distortion especially if your  settling is not a 1st order type  (1-e^(-t/TAU)).

Have you look at your clock generation circuit waveforms as well ? nice and cleanly spaced ?

hi, all
   Thx for your replies!
   I confused the input signal and the sampled signal just as Berti said. Now the linearity of the input switch is the key problem, and I found that a boot strapped switch will solve it for instance the configuration mentioned in M. Dessouky and A. Kaiser's paper in 1999.  

regards,
      pilo