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Using transient noise for PLL and ADC (Read 19233 times)
joebob
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Using transient noise for PLL and ADC
Dec 01st, 2009, 4:36pm
 
Transient (time-domain) noise is a worthwhile option to use simulating the phase noise for PLLs and also looking at the device noise contribution for other designs such as ADCs where noise can affect frequency sensitivity and calculations for  SNR, SFDR, etc... One question that comes up is what should be the fmax for a simulation?  What is realistic to consider? 2X? 50X?  The same for fmin. For example, some ADC can work at the audio range and therefore fmin should be set for that. Also, if anyone has used transient noise and have found it worthwhile, what are your experiences and results?
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Mayank
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Re: Using transient noise for PLL and ADC
Reply #1 - Dec 1st, 2009, 9:06pm
 
Hello ramullen,
    Quote:
One question that comes up is what should be the fmax for a simulation?
Fmax is generally kept as 50x the Oscillation Frequency or the steady-state frequency of your system to take noise contribution from harmonics into account.

Fmin -- i am also not too sure about that....leave it default for now...I think it should be the minimum frequency offset at which you want phase noise.

Quote:
Also, if anyone has used transient noise and have found it worthwhile, what are your experiences and results?

My personal opinion -- If you are planning to do tran-noise run & then take a DFT for phse noise....It takes a very very long time to do a transient noise run (spectre stats on a quad-core 8GB server - around 1 day/1ms run) -- not worthwhile.....Just do a pss-pnoise instead....frequency domain simulator is much faster...
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pancho_hideboo
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Re: Using transient noise for PLL and ADC
Reply #2 - Dec 5th, 2009, 3:49am
 
I can't find out any Design Issue in your post.
Please post to Simulator's Boards.

Mayank wrote on Dec 1st, 2009, 9:06pm:
joebob wrote on Dec 1st, 2009, 4:36pm:
Also, if anyone has used transient noise and have found it worthwhile,
what are your experiences and results?
My personal opinion --
If you are planning to do tran-noise run & then take a DFT for phse noise....
It takes a very very long time to do a transient noise run
(spectre stats on a quad-core 8GB server - around 1 day/1ms run)
-- not worthwhile
.....Just do a pss-pnoise instead....frequency domain simulator is much faster...
I don't think so.
Transient Noise Analysis is mandatory rather than worthwhile especially for Delta-Sigma-ADC and PLL.

I don't think small signal noise analysis in frequency domain is useful for Delta-Sigma-ADC and PLL
because small signal noise never affects nonlineality which is a key role in Delta-Sigma-ADC and PLL.

Previously Cadence has claimed same opinion just as yours.
Cadence has strongly denied Transient Noise Analysis over long long time.

Instead Cadence advertised pnoise(type=timedomain) which is no more than small signal analysis in frequency domain and is very very limited regarding applicable circuits and behavioral models.
http://www.designers-guide.org/Forum/YaBB.pl?num=1258339986

But Cadence is advertising Transient Noise Analysis intensively now.
This situation is also very true for HB Analysis, Convolution, Bsources and needs for multiple noise outputs ability, etc.
Cadence has strongly denied them over long long time.

About Transient Noise Analysis, I think performance of the following two simulators are superior than other simulators, of course far superior than Cadence Spectre.
   - Berkeley Design Automation AFS Transient Noise Analysis
      http://www.berkeley-da.com/prod/prod04_afs_tn.htm
   - Ansoft NEXXIM
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« Last Edit: Dec 5th, 2009, 5:35am by pancho_hideboo »  
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currant
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Re: Using transient noise for PLL and ADC
Reply #3 - Dec 6th, 2009, 2:14am
 
 We extensively use tran analysis with noise option when analyse delta-sigma ADC, fractional PLL, and nonlinear circuits with large input signal (when pss does't converge).
But sometimes we have  incorrect results.  Look at this  post
http://www.designers-guide.org/Forum/YaBB.pl?num=1256737141
 Furthermore spectre needs so much time to simulate big circuit with proper noise setup (big Fmax and long simulation time for small Fmin).
 Recently  I evaluted BDA AFS simulator and results (SNR) seems much more correct than from spectre, and simulation  is 4-6 times faster (perhaps only in this specific circuit) .
 
 About Fmax. If we consider ADC, then we must  set correct fmax to account noise folding, in my opinion, fmax is depended on equivalent noise bandwith (ENB) of S/H circuit.
 I usually set Fmin from simulation time (1/tstop), and simulation time is based on bandwidth and resolution of my spectrum.
 But, I think, if You need correct phase noise spectrum, tstop will more than 1/fmin (fmin, in this case, is a minimum offset  .
 From BDA  docs we have following recomendations:
    noisefmax≥50*VCOfreq, noisefmin=10/tstop, tstop=tstabilization+40-100 periods of minimum freq offset from carier.

 Best regards.
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