hi yawei,

Quote:
I agree to the fullest.

Quote:
I also have the same confusion of converting phase noise PSD in Freq Domain to Jitter in Time Domain. I think Pancho was pointing to this confusion.
 My Explanation --
1.   How to set limits of integration in Freq Domain for integrating PLL Phase Noise plot (which follows PD b4 BW & VCO after BW) to obtain Jitter ??
2.   And I believe the metric(cycle-2-cycle / long-term period jitter) of this Jitter obtained through this method depends upon the Limits ofIntegration.  
3.   According to me, If you integrate your PLL phase noise Plot ,
         a.>  From a very low freq( by low i mean below Linewidth of Osci) to Fosc/2 -- The Phase Noise plot is no longer Lorentzian below Linewidth & that Phase noise is because of Flicker Noise. The Jitter that we calculate by this integration will give us the Long-Term k-cycle Period Jitter including the Slow Drift/Wander in the PLL Output.
        b.>  From a Freq above linewidth to Fosc/2 -- The Phase Noise plot is totally Lorentzian. & The Jitter that we will get through this integration would indicate Long-Term k-cycle Period Jitter without any effects of Drift / Wander Included.
        c.> Cycle-to-Cycle Jitter -- Pnoise value at an offset greater than Linewidth, where Lorentzian assumption holds true, when converted to time domain through Lorentzian small signal assumption frmula gives C-2-C Jitter. Here, we dont integrate because we are considering adjacent Cycle Jitter. Integration means memory effects means Long-Term Jitter.
 

Pls feel free to comment [ /compliment  ;) ]

Hi all,

Interesting discussion but I think it misses the answer to the original question.

I would approach the problem in a different way:

What you get in the ADC output spectrum basically results from reciprocal mixing between the ADC input signal and the phase noise of your clock. The problem is however that for ADC the required jitter is typically specified as jitter, while for PLL/VCO design it is more convenient to know the required phase noise. Demir has published a couple of papers where phase noise of a PLLs is related to jitter. These equations use cycle jitter (self-referred) as the equation should remain valid as the PLL loop bandwidth goes towards zero. But that no problem at all because as long as the clock frequency is much larger than the PLL loop bandwidth: Jc ≈ √2×Jee (Jc : cycle Jitter, Jee : edge-to-edge Jitter).

That means:

1.) Use the simple formula the estimate the required Jee.
2.) Calculate Jc and translate that into phase noise requirements.
3.) Start designing your PLL.
4.) Once you can use simulations (pnoise), the simulator can calculated the desired jitter metric for you.


Regards

Hi David,

You are right, but I think you miss the point.
The jitter specifications obtained for the ADC need to be related to the clock source. In the case of a PLL phase noise specifications are required for block level design. In this case, aperture jitter is typically not very useful....unless you solely rely on simulations.

Cheers