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If your bias is broadband ie contributes noticeable noise at 1xLO and 2xLO etc then these noise sources will either feed through or be harmonically converted. Then in this case filtering of the bias will help, additionally you may externally regulate (external since cap on chip usually is prohibitively large), you may be able to knock down the 0XLO related noise or atleast push them low enough to be reduced by the PLL loop.
Also, Consider a differential GM type of oscillator, a considerable amount of noise can be attributed to 2xLO and other even order harmonic mixing at the common source. This often gets worse when the current increases due to the impedence being lowered at the common source. This is commonly eliminated by adding a resistor or some frequency selective high impedance circuit such as a LC tank. Finally, VCO phase noise improves when the voltage of the oscilation increases and not only the current increases, If you increase the current and the amplitude of the oscilation only slightly increases then phase can be worse not better.
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