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AnalogDE

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Designing a VDD/2 reference (rail splitter)
Dec 21^st, 2009, 10:55pm

Hi,

I'm designing a VDD/2 reference that splits a 1.5V supply. Error needs to be ~1mV or less, and the generator needs to be low impendance.

One way to do it:
I could use a simple resistor divider, but I need switches in series with the divider to turn it off when not in use... These switches will contribute a Resistance->Voltage error... Does anyone know of any schemes to try and cancel the error contribution from the switches?

If anyone can think of any other good schemes, lemme know.

Thanks!

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wave Senior Member Offline Posts: 117 Silicon Valley	Re: Designing a VDD/2 reference (rail splitter) Reply #1 - Dec 22^nd, 2009, 9:44am So does this mean your supply is as clean as 2mV, or are you drinking too much egg nog? You probably need a trimmed BG Reference and a fraction of that. Wave
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AnalogDE Senior Member Offline Posts: 137	Re: Designing a VDD/2 reference (rail splitter) Reply #2 - Dec 22^nd, 2009, 10:49am wave, Actually the error should be specified from the ideal VDD/2 output -- this reference voltage needs to track the supply. So it can't be BGV-based. The error should be small.
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AnalogDE

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Re: Designing a VDD/2 reference (rail splitter)
Reply #3 - Jan 7^th, 2010, 5:41pm

I've convinced myself that the switch device doesn't make a big deal -- since its resistance is small compared to the ladder it has a negligible effect on the output voltage (vs process and vs temp)

I need very fine steps -- ~2mV range. With a 1.5V input voltage, that's 1.5V/2mV = 750 segments. I need the 2mV step size to only correct for variation from the ideal midpoint value, so quantization error is ~1mV max.

In order to cut down on the large number of (small L) segments, is it possible to group into fewer segments near the rails (with larger L) and use the smaller segments around the midpoint to correct for process variation? I am using poly resistors.

Anything I should watch out for here?

Thanks!

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Designing a VDD/2 reference (rail splitter) Reply #4 - Jan 8^th, 2010, 1:17pm that is an awful lot of fanciness to get a mid scale voltage. A thousand odd resistors will eat up a lot of space. suggest you look at your system and ask why does a mid scale reference need to be so bloody accurate?
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eecs4ever New Member Offline Posts: 7	Re: Designing a VDD/2 reference (rail splitter) Reply #5 - Feb 24^th, 2010, 11:59am hi, see attached picture
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eecs4ever New Member Offline Posts: 7	Re: Designing a VDD/2 reference (rail splitter) Reply #6 - Feb 24^th, 2010, 12:07pm to be able to turn off the R ladder, we need some series switches. If this VDD/2 node doesnt draw DC power, then we can use a structure shown below. As long as we make the nmos / pmos resistance small enough compared to the resistor R value. Only 10% matching between the N and P is required.
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AnalogDE

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Re: Designing a VDD/2 reference (rail splitter)
Reply #7 - Feb 24^th, 2010, 5:54pm

Thanks eecs4ever.

Right now what I have is just a very large NMOS at the bottom of the ladder (without the PMOS in your scheme). I like your scheme because if the N and P switches are sized to have roughly equal resistance, then the tap point is right at the center, whereas in my scheme I have to compensate for the NMOS IR rise. Are there any other advantages?

I'm wondering if your scheme suffers from more variation at cross corners (slow P, fast N and vice versa). I guess this is mitigated by having them quite large.

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eecs4ever

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Re: Designing a VDD/2 reference (rail splitter)
Reply #8 - Feb 25^th, 2010, 9:17pm

Hi Jiesteve,

I think its fine either way, as long as your resistance is dominated by the resistor R. Keep the mosfets large so that its variation doesn't hurt your accuracy.

One thing to keep in mind is that mosfet do have gate leakage, especially for the thin-oxide devices in the lower technology nodes. When you are trying to lower the ON resistance, its probably you will need a very large transistor. simulate the gate leakage and make sure it doesn't hurt you. Gate leakage tend to have large variations from run to run and varies exponentially with temperature and voltage.

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loose-electron

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Re: Designing a VDD/2 reference (rail splitter)
Reply #9 - Feb 26^th, 2010, 1:53pm

NMOS and PMOS do not scale together and do not track each other

AnalogDE wrote on Feb 24^th, 2010, 5:54pm:

Thanks eecs4ever.

Right now what I have is just a very large NMOS at the bottom of the ladder (without the PMOS in your scheme). �I like your scheme because if the N and P switches are sized to have roughly equal resistance, then the tap point is right at the center, whereas in my scheme I have to compensate for the NMOS IR rise. �Are there any other advantages?

I'm wondering if your scheme suffers from more variation at cross corners (slow P, fast N and vice versa). �I guess this is mitigated by having them quite large. �

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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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