I want to use the pnoise (spectreRF) to analyse the noise of a Switched-Capacitor SH Circuit in Pipelined ADC. Fig 1 in the attachment shows the testbench I set up. The operation frequency CKSH is 50MHz. Vsource and ideal_balun are used to generate the differential signal and the R, C connnect to the output of SHA are the equivalent loads.
Fisrt, I do pss+pac+poise analysis
the Vsource is set as follows:
VIN (net021 GNDA) vsource dc=0 type=dc pacmag=1
I use the "Direct Plot" to display the results which are shown in Fig2. There're 2 things I have confusion in this result.

1. The tranfer function shows that the low frequency voltage gain is only 0.5, (Both pac and pnoise analysis). But the exact voltage of a SHA circuit should be about 1. Why?
  I tried doing only pss analysis to see whether the signal is attenuated by 6dB. This time I set the Vsource and pss as:
VIN (net021 GNDA) vsource dc=0 type=sine freq=5M ampl=300m
pss pss fund=5M harms=10 errpreset=conservative tstab=400n maxacfreq=6G annotate=status
Fig 3 and Fig 4 shows the results I got.
Fig 3 shows the harmonic of three differential signals: (net021 GNDA) which is the Vsource, (VINP VINN) which is the output of ideal_balun, (VOP VON) which is output of SHA. There is exactly a 6dB attenuation at the output. I don't know why?
Fig 4 is the time-dominal results of pss. The top graph contains the differential input and output signal and it shows that the output follows the input signal very well (both are 288mV as the cursors show). So why comes 6dB attenuation??

2. In Fig 2, the input noise is 6dB larger than the output noise (It's must due to the attenuation ), otherwise they're expexted to be almost the same for the SH circuit with gain 1. Another thing confused me in Fig 2 is the spectrum peak at 100MHz, 2X the clock frequency.
I know that spectrum folding could cause this kind of peak naturally, but shouldn't the peak locate at 0.5X clock frequency, i.e 25MHz in this case? or I have a misunderstanding? please let me know.

Some additional information may help to locate the problem. The SH adopts flip-around architecture and I have analysed the SH  by .tran analysis and do FFT in matlab, the results shows that the dynamic performance of the SH meet the specification. Fig 5 shows the result of tran analysis. So it seems there is little chance that somehing is wrong with circuit itself and probably something is uncorrect in my noise simulation.

I'm sorry the post is kind of long, I just want to describe the problem clearly. Hope I did it.
Thanks to your guys and Merry Chirstmas in advance.

Thank you Ken!

If so, may I assume that the output noise is reasonable and the input noise just doesn't make sense beacuse it's ralted to the signal duty. I should integrate the output noise and calculate the input-referred noise myself.


Again the sencond confusion. Could someone explain to me the spectrum peak at 100MHz.Is it relted to the spectrum folding as I understand so far?
I'm not sure if the ENBW is higher than 100MHz in my case.(I just know some thing about ENBW, like the ENBW of single-pole system which is about 0.5*pi*BW. I'm searching some material about the ENBW of Pipeline ADC, some reference recommended by your guys would be appreciated.)
If 100MHz is in the ENBW in my case,  the integrated noise could be very large.

Thank you Ken!

I reread the paper and make some modifiction to my original testbench, a sh without hidden state(mentioned in the paper) is introduced to sample the output of the real SH circuit. So the testbench goes to Fig 1 in the attchment. I tried the linear frequency sweep and set the pss and pnoise simulation as follows.
pss  pss  fund=50M  harms=0  errpreset=moderate  tstab=400n
+    saveinit=yes  tstabmethod=gear2only  maxacfreq=3G  annotate=status
pnoise  (  VOP  VON  )  pnoise  start=0.5M  stop=300M  step=0.5M
+       maxsideband=10  iprobe=VIN  refsideband=0  annotate=status

and the result in Fig2 and Fig 3 show that
1) the transfer function becoms 1 in low frequency and is a sin(x)/x function through the frequency range as expected. So the previous gain result is due to the signal duty indeed.
2) When linear sweep the frequency, the spetrum peak in output noise curve has gone but there is still a peak in input noise curve and this time it moves to the frequency  of 50MHz (1X the clock frequency) . When log sweep the frequcy, the spetrum peak in output noise curve has gone but there is still a peak in input noise curve and this time it moves to the frequency  of 100MHz (2X the clock frequency) .

Three points here confuse me
a. Why the spectrum peak in the output noise disappear but the the peak in the input noise spectrum remain? It seems related to the ideal sh that I added for test. Since I resimulated the testbench without ideal sh and the input/output noise curve both have peaks at 100MHz(2X the clock frequency).
b. Why linear sweep the frequency and log sweep the frequency got the peak at the different frequency?
c. I tried to find something between the Input/Output noise curve and the gain curve at the peak point. It shows that at 50MHz
input noise(IN): 3.16e-6 V² /Hz
output noise(ON): 6.43e-22 V²/Hz
gain(G):            9.2e-6
They don't meet the formula IN=ON/G²,in fact ON/² is about 760e-6 V²/Hz.Shouldn't they meet the formula because in the frequency area without peak IN is almost the same with ON, and approximatly meet the formula.


3) The noise summary is shown in Fig 3 and tells that flicker noise contributes 1.68 percent. But how to check whethet the peak is caused by  flicker noise or not? Please give me some tips.
As expected the noise are almost controbuted by the MOS transistor in the OTA of the SH. Fig 4 shows the structue of the OTA--folded cascode with hybrid cascode compensation. some trivial thing is ommitted for simplification.

4) Since the models for simulation are too large to upload, I attach the netlist only (File tb_SHA_noise.net) to help locate the problem.

--BackerShu

The flicker noise is mixed up to multiples of the clock frequency, creating spikes every 50MHz. However, these spikes are very narrow. Furthermore, if you evaluate at exact multiples of the clock frequency, the flicker noise would be infinite, and so is ignored. The frequency sweeps you are using are dramatically undersampling these spikes, so sometimes you see them, and sometimes you do not. If you want to examine them closely, sweep k×f₀±Δf, where k×f₀ is some harmonic of the clock frequency, and Δf is small enough to see the flicker noise, say 100kHz.

The cause of peaks in the input referred noise that occur when there is no peak in the output noise are due to nulls in the gain. Since the gain is going to zero at these frequencies, the input referred noise must go to infinity in order to see a finite output noise.

-Ken