BackerShu
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I want to use the pnoise (spectreRF) to analyse the noise of a Switched-Capacitor SH Circuit in Pipelined ADC. Fig 1 in the attachment shows the testbench I set up. The operation frequency CKSH is 50MHz. Vsource and ideal_balun are used to generate the differential signal and the R, C connnect to the output of SHA are the equivalent loads. Fisrt, I do pss+pac+poise analysis the Vsource is set as follows: VIN (net021 GNDA) vsource dc=0 type=dc pacmag=1 I use the "Direct Plot" to display the results which are shown in Fig2. There're 2 things I have confusion in this result.
1. The tranfer function shows that the low frequency voltage gain is only 0.5, (Both pac and pnoise analysis). But the exact voltage of a SHA circuit should be about 1. Why? I tried doing only pss analysis to see whether the signal is attenuated by 6dB. This time I set the Vsource and pss as: VIN (net021 GNDA) vsource dc=0 type=sine freq=5M ampl=300m pss pss fund=5M harms=10 errpreset=conservative tstab=400n maxacfreq=6G annotate=status Fig 3 and Fig 4 shows the results I got. Fig 3 shows the harmonic of three differential signals: (net021 GNDA) which is the Vsource, (VINP VINN) which is the output of ideal_balun, (VOP VON) which is output of SHA. There is exactly a 6dB attenuation at the output. I don't know why? Fig 4 is the time-dominal results of pss. The top graph contains the differential input and output signal and it shows that the output follows the input signal very well (both are 288mV as the cursors show). So why comes 6dB attenuation??
2. In Fig 2, the input noise is 6dB larger than the output noise (It's must due to the attenuation ), otherwise they're expexted to be almost the same for the SH circuit with gain 1. Another thing confused me in Fig 2 is the spectrum peak at 100MHz, 2X the clock frequency. I know that spectrum folding could cause this kind of peak naturally, but shouldn't the peak locate at 0.5X clock frequency, i.e 25MHz in this case? or I have a misunderstanding? please let me know.
Some additional information may help to locate the problem. The SH adopts flip-around architecture and I have analysed the SH by .tran analysis and do FFT in matlab, the results shows that the dynamic performance of the SH meet the specification. Fig 5 shows the result of tran analysis. So it seems there is little chance that somehing is wrong with circuit itself and probably something is uncorrect in my noise simulation.
I'm sorry the post is kind of long, I just want to describe the problem clearly. Hope I did it. Thanks to your guys and Merry Chirstmas in advance.
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