Dear All,
             For  Deep n-well nmos I like to connect the nwell to VDD to have the maximum RW-NW reverse bias and so minimum RW-NW junction capacitance. I  avoid to connect the NW to DIGITAL_VDD as it will directly  inject nois. But I'm still paranoid considering the potential noise injection even from VDD_ANALOG pin into the nw. So is it wiser to leave the nw floating ??? Or is there some other smarter  practice ???

Agree with vivek. Tie it to the analog VDD, may be through an integrated RC network for filtering high frequency VDD components.
Since there is no DC consumption such RC network will not affect NW biasing.

Tosei

In addition to the other good advices you have received, I suggest you focus on what devices you want to protect from substrate noise.  

For example if you want to protect the p-mos transistors inside the n-well, then you want to reduce the noise coupling through backgate modulation and capacitive coupling through drain and source reversed biased junctions.  Thus, you want to connect the n-well to the same positive supply that powers these p-mos transistors and through a very low resistive/inductive path and using multiple n-well contacts (no RC filter here).  

You can analyze similar cases in a similar way, by first identifying the coupling mechanisms.  An RC filter for example will block some frequency components of the noise, but before you implement it I suggest you identify what noise you block, where it is coming from, and what is the impact of how do you block it (charge displacement in the capacitor generates transient currents; where do they go)

Cosmin Iorga, Ph.D.
NoiseCoupling.com
http://www.noisecoupling.com