Hi folks,
     Ken in his paper on PLLnoise + Jitter introduces two variables in VerlogA Model of an VCO+FDN ---- Accumulating Jitter  &  Synchronous Jitter.
         I Guess Accumulating Jitter comes from VCO  & Synchronous Jitter is Jitter of Divider.

Question 1 :---  Which of these metrics define the Single Period Jitter of the Clock if I tap my Output at VCO Output ??

Question 2 :--  What is the correlation between these variables used in VerilogA Model [ Accumulating Jitter  & Synchronous Jitter ]  and actual Jitter Metrics [ Single Period Jitter & Cycle-to-Cycle Jitter ]

Question 3 :--  In one place, it is stated that Synchronous Jitter represents Edge-to-Edge Jitter of the Clock....What is the relation between Edge-to-Edge Jitter and Cycle-to-Cycle Jitter ?

 Question 4 :-- How to calculate Edge-to-Edge Jitter of PLL Output Clock when i have it's transient data for a long time(say 100us) ??

It would be very helpful if someone could help in clearing these doubts.

--
regards,
Mayank.