Dear All,

I am trying to follow Ken's article "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers" and to build a PLL (Integer-N) behavior model to get the pll phase noise performance.

When extracting the jitter of PFD/CP, I got 656ns. Is it reasonable?

After running Pnoise simulation for PFD/CP, I got
-96.1dBc/Hz @ 10Hz
-106.6             100
-116.8             1K
-126.2             10K
-132.9             100K
-134.8             1M
-135.3             10M

I got var(n) which is 6.6e-7 by formula (57) in the article.
The current of CP is 25uA and the frequency of PFD is 35MHz.
According to formula (58), I got 656ns.
I think it is really a large number.
Is there any problem in my calculation?

Please help me~~

Thanks,

Chris  

sorry for reposting.
I just thought the content is more proper for this category.

BTW, does anyone do well on PFD/CP jitter extraction?

I still can not get a good result.