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refugee

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Is my calculation correct?
Jan 21^st, 2010, 5:57am

Hi, all
I'm designing a simple LDO which will set the output as the main pole point.
The main chanllenge is that the LDO should response quickly but with relatively small error(10mV). And the LDO should have the capacity of driving 3A current.
So, my calculation is:
The output resistance is about: 0.75/3A=0.25 Ohm
The DC gain should be: 750m/(10mv-5mv)=150=44dB
To get a 1us 10%~90% rising time, the GBW should be: 350kHz

So, the main pole is: 350K/150=2.33kHz
The the cap should be: 273uF

is my calculation correct?

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raja.cedt

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Re: Is my calculation correct?
Reply #1 - Jan 21^st, 2010, 7:28am

hi refugee,
actually it is very difficult to make outpole dominate at leat in this type of architecture due to the low Zat the output, infact this demands very big cap at the o/p at the same time too large opamp BW.
comming to you calculations, 1.for o/p resistance you have to use voltage ripple instead of .75 3.so for finding o/p cap also you have to use small signal R rather large signal R..by the way is it onchip ckt or off chip ckt.

Thanks,
Rajasekhar.

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refugee

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Re: Is my calculation correct?
Reply #2 - Jan 21^st, 2010, 3:24pm

raja.cedt wrote on Jan 21^st, 2010, 7:28am:

hi refugee,
� � actually it is very difficult to make outpole dominate at leat in this type of architecture due to the low Zat the output, infact this demands very big cap at the o/p at the same time too large opamp BW.
� comming to you calculations, 1.for o/p resistance you have to use voltage ripple instead of .75 � 3.so for finding o/p cap also you have to use small signal R rather large signal R..by the way is it �onchip ckt or off chip ckt.

Thanks,
Rajasekhar.

hi, RAjasekhar.
because this ckt is used as power supply for some high speed digital ic. so, the stability is very important. I think set the output as the main pole is the only choise.(Because we can not integreted a large cap inside the chip)
And, would you please tell me how to calculate the ouput res and open loop gain for this 3A DC output case?
ps. the amp and pass device are integrated inside the chip. the cap is the outside component. the 5mV is the ramdon offset.

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Is my calculation correct? Reply #3 - Jan 21^st, 2010, 8:05pm hi, for 3ma change in the current load how much ripple you can tolerate, this is the small signal o/p res which is equal to 1/(A*Gm)..with this exp people used to find A (of course gm is there from load quesent current) Thanks, Rajasekhar.
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refugee

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Re: Is my calculation correct?
Reply #4 - Jan 22^nd, 2010, 10:26pm

raja.cedt wrote on Jan 21^st, 2010, 8:05pm:

hi,
� for 3ma change in the current load how much ripple you can tolerate, this is the small signal o/p res which is equal to 1/(A*Gm)..with this exp people used to find A (of course gm is there from load quesent current)

Thanks,
Rajasekhar.

Hi, Rajasekhar
I really appreciate your kindly help.

I hope that for maximum load to no load condition, the output should be stable (that means dc output).
And I agree with you about the small signal output res. But is that means that to get such a main pole with this kind of compensation method, I need even more cap at the output?

And, for the gain part, could you please tell how many small signal gain and dc gain should I get to meet the requirement of the accuray?

Thanks again.
refugee

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Is my calculation correct? Reply #5 - Jan 23^rd, 2010, 1:35am hi, you can get many basic things regarding regulator in the following site. http://users.ece.gatech.edu/rincon-mora/publicat/ Thanks.
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