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Maks

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Capacitance matching/weighting in precision analog circuits?
Jan 31^st, 2010, 12:48pm

Many precision analog circuits rely on perfect capacitance matching or weighting (i.e. binary weighting). However, even "good" layout techniques do not guarantee perfect matching. Remaining parasitic coupling (at the level of 1%, 0.1%, or 0.01% of the total net capacitance) may be difficult to eliminate, but it may lead to deterioration of circuit performance (linearity, offset, etc.).

Are there any common practical approaches to resolve minute parasitic coupling and to eliminate them? Are there any methodologies, or existing CAD solutions?

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loose-electron

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #1 - Feb 1^st, 2010, 6:01pm

beyond good layout techniques (symmetry size interleaving of arrays) thats about it.

There are ways of doing variable capacitors (varactors depletions depth, switching of arrays) but I dont know of anyone using a simple way to tweak fixed value devices

people have used link blowing to tweak capacitor size,. and laser trimming to cut slices off of the sides of caps but its not in wide use any more.

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vivkr

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #2 - Feb 2^nd, 2010, 5:13am

Maks wrote on Jan 31^st, 2010, 12:48pm:

Many precision analog circuits rely on perfect capacitance matching or weighting (i.e. binary weighting). However, even "good" layout techniques do not guarantee perfect matching. Remaining parasitic coupling (at the level of 1%, 0.1%, or 0.01% of the total net capacitance) may be difficult to eliminate, but it may lead to deterioration of circuit performance (linearity, offset, etc.).

Are there any common practical approaches to resolve minute parasitic coupling and to eliminate them? Are there any methodologies, or existing CAD solutions?

There are many design methodologies for making your circuit immune to such imperfections, which primarily find application in data converter circuits where such imperfections manifest themselves in form of nonlinear distortion. Broadly speaking, the following types of methods exist (I am using ADCs as an example class of circuits but similar methods should exist for all/most kinds of circuits):

1. Architectural choices: At a higher level of design, you may choose a scheme which is inherently insensitive to mismatch or where mismatch will give you a more benign error such as offset, gain error instead of nonlinear distortion, e.g. using a single-bit delta-sigma ADC instead of an SAR for realizing higher accuracy.

2. Error cancellation schemes: At a slightly lower level of design you use schemes where error balancing or error cancelling is performed. There are several such schemes for SAR type ADCs where a single amplification process is performed multiple times in order to generate all possible mismatch terms and then combine them to cancel out the errors, e.g. see the paper below and the references contained therein
http://web.engr.oregonstate.edu/~moon/research/files/iscas99_sar.pdf

3. Error calibration: The mismatch-induced errors are measured in foreground or background and a correction term applied. There are dozens of examples of this. Just look in the literature.

4. Error randomization: Using dithering or rotating and averaging usually allows improvements in the spectral characteristics of the error, decoupling it significantly from the signal.

5. Designing your circuit in a manner that it operates at the sweet spot where it is least sensitive to mismatch. This point while obvious is the one most likely to be missing in the run-up to most designs. Circuits which are sensitive to mismatch usually are not equally sensitive to mismatch under all conditions. You need to find the best conditions.

If all else fails, then you maybe need to ask yourself why the excessively high levels of matching are needed. Perhaps this should be asked at the beginning.

Vivek

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Maks

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #3 - Feb 3^rd, 2010, 12:10pm

Vivek -

thanks for your detailed explanation of circuit/design techniques that help to reduce or eliminate capacitor mismatch effect. Actually, I was asking about eliminating mismatch at the layout level - which would make the life much simpler (I am pretty sure that the techniques you mentioned will lead to increase of chip area, or power, or reduce speed, etc. - i.e. they are not coming for free).

Jerry -

thanks for your feedback. This is what I suspected (I am not a circuit designer, so I wanted to hear an expert advice).

There was a nice article about capacitor matching, offering very specific "good layout" suggestions to avoid (systematic) mismatch:
M.J.McNutt et al., "Systematic capacitance matching errors and corrective layout procedures", IEEE J. Solid State Circuits, v.29, no.5, 1994, p. 611-616.

It listed five major layout factor affecting matching:

1. mismatched perimeter ratios
2. proximity effects in unit capacitor lithography
3. mismatched long range fringe capacitance
4. mismatched interconnect capacitance
5. parasitic interconnect capacitance

Other than item (2), all of these factors are caused by parasitic capacitances.

The suggestions offered in that article are very difficult to follow in practice �for several reasons - the real layouts are too complex to see all the parasitic coupling by an eye inspection, the area is very often constrained so that it's hard to create identical capacitive environment for all unit capacitors, etc.

If there would be a software tool that would allow a designer to calculate all the parasitic (as well as intended) capacitances with a very high accuracy - I am talking about accuracy level of 1%, 0.1%, or 0.01% (or better) of the total net capacitance - so that a designer can quickly capture the problems of the layout, and optimize layout so as to eliminate parasitics, or make them matched or weighted with the same retios as intended capacitors, as well as to get a precise capacitive model of the design - would that software be useful for precision analog design?

I guess that answer should be "yes", but I would like to hear an expert opinion on this.

Thanks,

� Max
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loose-electron

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #4 - Feb 3^rd, 2010, 2:44pm

Maks - the article from 1994 that you cite seems to mention many of the classic good practices used in this area.

LPE (layout Parasitic Extraction) is available as an EDA tool to determine parasitics in layouts (duh! like the name doesnt say that? �:o )

However, brute force LPE on big circuits is not practical, its useful in small controlled situations (a mixer in a RF receiver is a good example)

Geometry, symmetry and the list from the paper are really the best you can get, �real world industry applications require that you provide alignment and calibration to get around the limits of mismatch. It becomes a big part of the design effort on pretty much anything of complexity.

Vivek has a good list there its pretty typical.

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Maks

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #5 - Feb 3^rd, 2010, 4:37pm

Jerry -

Yes, you are right that LPE (parasitic extraction) EDA tools can "extract" (or calculate) parasitic capacitances. And they can extract full chip. However, (almost) all "industry-standard" extraction tools are not rigorous field solvers - i.e. they do not solve (Laplace) equation for the electrostatic potential to calculate capacitances from the first principles.

These tools are based on so-called "pattern-matching" approach, where they use a field solver (Raphael or similar solver) to generate a database with capacitance values for some metal combinations (i.e. parallel or perpendicular fingers with varying width and spacing, in different metal layers, with or without top and/or bottom groundplane). Then, when they extract a design/layout, they fracture it into elements and try to match the metal combinations with those available in the database. However, capacitance is a nonlinear characteristic, and can not be calculated accurately by simple fracturing and different component combination.

As a result, pattern-matching based tools can give you only an approximate value of the capacitance, that can be 5-10-20 percent different from the real value of the net capacitance, and this error is not controllable. In particular, when you do metal layout change, the change in extracted capacitance may not be predictive. Furthermore, small coupling capacitance values (say 5% o f the total net capacitance and below), as well as long-range capacitance coupling components may be missing.

The approximate extraction results may be OK for digital designs, but they are not enough for precision analog design - where capacitance matching/weighting requirements may be on the scale of 0.1-0.01% of the total net capacitance.

I believe that having a tool that can extract the whole layout with predictable and user-controllable accuracy on the scale of 0.1-0.01% should be very valuable for analog design.

Would you agree?

� Max

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vivkr

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #6 - Feb 4^th, 2010, 12:42am

Maks wrote on Feb 3^rd, 2010, 12:10pm:

Vivek -

(I am pretty sure that the techniques you mentioned will lead to increase of chip area, or power, or reduce speed, etc. - i.e. they are not coming for free).

1. mismatched perimeter ratios
2. proximity effects in unit capacitor lithography
3. mismatched long range fringe capacitance
4. mismatched interconnect capacitance
5. parasitic interconnect capacitance

Thanks,

Max
---------

Hi Max,

Indeed, all circuit level techniques will come at a cost. In terms of layout level optimization, I can suggest one tactic which I had to use myself in order to eliminate systematic parasitic and interconnect mismatch. The basic idea would be to build all matching-critical caps out of entirely shielded unit elements.

So if you were to make a poly1-poly2 cap, then the unit element cap would be surrounded on all sides by a poly1 and poly2 shield, plus metal1-metal(x-1) with top/bottom connections taken in metalx going in opposite directions. You would also add a shield in metalx leaving small openings at the ends for the connections to be drawn out.

In addition, you would then need to ensure that subsequent routing with the nets is performed in a way as to eliminate long-range parasitics from adding mismatch, and of course you need to consider other good design practices such as common-centroid layout etc. We used similar techniques to successfully design 14b-linear ADCs requiring no mismatch calibration.

Nevertheless, you pay a price here too. You will have enormous effort in making the layout and optimizing it until you get everything right, plus considerable parasitics which will require more power in whatever circuitry is driving those. Consider that there is practically no way to eliminate mismatch between parasitic caps from far away except by providing a "shunt" to a closer low-ohmic connection, i.e. more parasitics even though these may be better matched and deterministic.

In my opinion, it is not worthwhile trying to strive for better than 0.1% matching at layout level. Circuit techniques provide a higher level of robustness at a smaller price than you might imagine.

Regards,

Vivek

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loose-electron

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #7 - Feb 4^th, 2010, 6:42pm

LPE is largely used by RF designers, not digital designers.

There are some simple pattern match tools that are used for digital, and similar that get used for RF. Timing extraction is a simpler animal.

First important thing - nominal Capacitances in a layout will change by +/- 20% (still a good guideline) due to process variance

If you need better than that on absolute value its not going to happen just due to semiconductor physics and foundry capabilities

If you need the accuracy you mention in matching of devices, again (0.01%!!!) its not going to happen and be a practical product - because the circuit architecture is too dependent on matching - there are many other ways of getting the job done that are more robust under yield loss issues

Extracting the "whole chip parasitics" is pretty useless. The simulation yields little useful information and takes forever to run. Frequently it never runs because the net is too complex for the simulator to solve. (within reasonable amount of time at least)

Where LPE is valuable is in small, well defined situations, not as a magic button to push that solves your system.

Getting 4 places of accuracy doesn't have a lot value when you need to allow for much wider variances. Geometry matching gets you to the limits of accuracy that are real, and not just a math and statistics exercise.

[quote author=Maks link=1264970938/0#5 date=1265243873
As a result, pattern-matching based tools can give you only an approximate value of the capacitance, that can be 5-10-20 percent different from the real value
The approximate extraction results may be OK for digital designs, but they are not enough for precision analog design - where capacitance matching/weighting requirements may be on the scale of 0.1-0.01% of the total net capacitance.

I believe that having a tool that can extract the whole layout with predictable and user-controllable accuracy on the scale of 0.1-0.01% should be very valuable for analog design.

[/quote]

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Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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Maks

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Re: Capacitance matching/weighting in precision analog circuits?
Reply #8 - Feb 17^th, 2010, 1:00am

Jerry, Vivek -

thanks a lot for your feedback.

It was my main idea - to avoid "enormous" efforts of making a perfectly matching layout using an "automated" EDA tool.

Even though absolute values of capacitance may change by say +-20%, the absolute accuracy in parasitic extraction still needs to be much higher (i.e. smaller in terms of percents) than that - on the scale of 0.1% or better - in order to guarantee a predictable and reliable extraction results, and to guarantee the "baseline" in extraction - i.e. the nets that are really matched should show very close capacitance in extraction.

Max
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