Mayank
|
Hi Steve, I fully agree with all the point that you just said....But seems like you didnt catch the methodology correctly....It uses the very same models that we use in simulations....I will explain. Gm/Id Methodology used Figures of Merits of a transistor, (roughly defining as the characterstics that are independent of MOSFET size). Steps involved in gm/id methodology --->
1. Simulate a single transistor (of certain width,not too small not too big say 1u in a 65nm Process) in spectre/spice...iterate and Store the DC operating point info (like ids,gm/id,id/w,gm/gds,etc...) for different Lengths, different corners of P & T, against full sweeps of vgs, vds, vbs and so on..... NOTE:-- This step gives you the transistor conditions directly from simulation, So if you a transistor happens to be in any ckt under those operating conditions, it will behave exactly the same as you simulated.
2. Formulate a mathematical model of your ckt, by writing KVL,KCLs at different nodes, taking into acc. as many parasitics as you can...Mathematical Tools come in handy here....
3. Optimize using mathematical tools & arrive at the best design point..Translate that point into Schematic/Spectre and get the simulation results...
For me, It matched with the simulations quite accurately for designs with UGB ~ 400MHz.....Never went upto GHz range of UGBs...
--Mayank
|