Hi guyz

I am designing an ASIC CMOS op-amp for meeting following design specs in TSMC .35um tech.
1. open-loop gain : 65-70dB
2. Unity gain frequency : 500MHz
3. Phase Margin ~ 60 degrees
4. Need an internal compensation technique.
5. 2 V p-p ODR

Can someone suggest me a configuration to be used.
Can this be achieved by using a standard folded cascode technique followed by a class AB output stage?

Thanks

Thanks a lot for your response . But can you suggest me any book or paper where i can actually build up a step-by-step procedure.
Actually the thing is that i have done quite a number of designs for the above specs. Phase margin never ever matches with what i design for.
But my hand calculations and simulated results are always way off.

I have tried designs from holberg, baker and martins

Can someone suggest me any other approach tht i need to take while designing op-amps.

Hi,
    I guess if your supply is 3.3V , then you need nt go for class AB o/p stage...You need it only if you want rail-to-rail o/p....Also keep in mind the i/p CM level is decided by the o/p CM level of the ckt preceeding your opamp...I always prefer fully differential topologies coz you hv CMFB control in your hands... Normal FC will do..

As for your design methodology, USE GM/ID ---Gives me excellent results !!!
          i guess you are using first order hand calculations using standard eqns....Use GM/ID methodology & try to make your analysis a bit more exact by including sec effects eg :-- parasitics consider Cgd & cdb along with Cgs....
In GM/ID, obtain plots for different lengths,vgs,vds,vbs,corners....Use those values to design your OTA...Keep design eqns as exact as possible...Use help of some mathematical tool like mathcad, matlab etc....

Feel free to ask anything else you want......
regards,
Mayank.

Hi both sos & carporsche,
                      As carporsche pointed out earlier, He was using hand calculations for design....Hand calculations, in which you mostly tend to include only 1st order effects, dont give accurate results...ex :-- parasitics like Cgd, Cdb which we generally tend to ignore in hand calcs to make maths easier affect the design a lot, say if you keep on increasing transistor size ignoring it's parasitic caps...

Trying to match your hand calculations with spectre results will require a lot of ckt tweaking....I would say avoid this spectre/spice monkeying...Go for Gm/Id methodology....if you want material, Just Google it, you will get many papers on it....and you will improve upon it as you go through a design following gm/id....

regards,
mayank.

Hi sos,
          Gm-by-Id is a graphical design technique which is based on technology plots of figures-of-merit simulated from a single MOSFET...That's why it gives you accurate results, provided your analysis is decent..You may take help of some mathematical tool like mathcad/matlab...I wish i had some material to share...Google it, surely you will find something on it....

--Mayank.

here's another file. i couldnt upload 2 files in the same post  .

Hii Steve,
                  My experience says gm/id graphical design methodology works best for even the most complicated design...I myself have done it for many operational amplifier topologies, ranging from a simple CS stage, normal 2-stage rz-cc compensated OTA, to more complex designs like class AB Folded Cascode opamp design, rail-to-rail i/p topologies, DAC current cells, current mirrors, bias ckts.....

    Gm/Id is by far the best design methodology i have come across....It requires analysis....but you can use tools like matlab/mathcad....But atleast you are sure you are designing the best point & that wotever you design will match with your simulations....

    What methodology do you have in mind ?


--Mayank

Hi Steve,
              I fully agree with all the point that you just said....But seems like you didnt catch the methodology correctly....It uses the very same models that we use in simulations....I will explain.

           Gm/Id Methodology used Figures of Merits of a transistor, (roughly defining as the characterstics that are independent of MOSFET size). Steps involved in gm/id methodology --->

1.  Simulate a single transistor (of certain width,not too small not too big say 1u in a 65nm Process) in spectre/spice...iterate and Store the DC operating point info (like ids,gm/id,id/w,gm/gds,etc...) for  different Lengths, different corners of P & T, against full sweeps of vgs, vds, vbs and so on.....
NOTE:-- This step gives you the transistor conditions directly from simulation, So if you a transistor happens to be in any ckt under those operating conditions, it will behave exactly the same as you simulated.

2.  Formulate a mathematical model of your ckt, by writing KVL,KCLs at different nodes, taking into acc. as many parasitics as you can...Mathematical Tools come in handy here....

3.  Optimize using mathematical tools & arrive at the best design point..Translate that point into Schematic/Spectre and get the simulation results...

For me, It matched with the simulations quite accurately for designs with UGB ~ 400MHz.....Never went upto GHz range of UGBs...

--Mayank