Hello Caporsche,
i have designed 2-stage OTA's with UGB in the range of 400 MHz or so......I didnt understand a few points in your post :--
1. What is the significance of id vs. (2*id/gm) Plot ??
2. I guess you did not take into account the cgd & cdb values....
In your plots, also use cdb/cgg & cgd/cgg plots....Then using the value of cgg found from fT/gm plot, you can find cdb & cgd....
Incorporate Cgd & cdb caps also into your calculations when you are working in 500 MHz range or above..... Use MATLAB to handle the complex expressions formed. You can also optimize the ckt using these plot values in any mathematical tool.
3. If you are sweeping vgs & vds completely uptil vdd, the values of gm/id in these plots are the maximum that you can attain in any circuit....I guess you probably meant
Higher Gm values for higher UGB requirements... ...
Once Gm/Id is sufficiently high, Increasing current is the only option we hv got 4. In some technologies, intrinsic gain of the transistor gm/gds is quite small....Increasing current increases Transconductance, but decreases gain at the same time...You might have to increase the length to keep gm/gds high....
5. GBW can be achieved easily by increasing the current...But If you are still not able to achieve the Gain requirements even after increasing lengths to acceptable values,
Revisit your topologyHope that answers you....
--Mayank