The followings are general notes for you.
-
Always describe vendor's name and tool's name which you use.
- Don't do multiple posts which are same content.
- Don't request source code or behavioral model without any efforts.
- There are many simulators which have analyses called as PSS, PAC and Pnoise.
- Describe in detail with using correct terminologies.
- Warnigns are different from Errors.
- ADS is not name of simulator.
- There is no tool which name is Cadence.
- Don't use Direct Plot of Cadence ADE blindly without knowing definition.
- All gains in Direct Plot of Cadence ADE are "right", "true" and "practical" voltage gain.
- Don't mix up Simulation with Post Processing. They are completely different phase.
- MATLAB are different from Simulink.
- Learn measurements using actual instruments. Not "EDA Tool Play
gabc wrote on Feb 19th, 2010, 10:20pm:Can anyone please tell me what is the meaning of vdd!*
vdd! is for global vdd
what does that mean? And what is vdd!*?
I assume you use Cadence Schematic Editor and ADE.
It means net name actually assigned for node using "Inherited Connection".
So it is no more than "vdd!".