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MOSFET LEVEL 3 verilogA model help! (Read 4702 times)
liletian
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MOSFET LEVEL 3 verilogA model help!
Mar 16th, 2010, 6:30pm
 
 Hi there
 Can anyone please give me a model VerilogA level 3 mosfet model? I saw the level 11 model, but I would like a simple level 3 verilogA model. The MOSFET should be 4 terminal devices.
 Thank you very much
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Geoffrey_Coram
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #1 - Mar 17th, 2010, 6:32am
 
Silvaco had created such a thing, free for non-commercial use.  I don't know if it's still available.

However, there's a problem with that model (level=3), because the equations are capacitance-based, not charge-based, and the capacitance equations can't be consistently integrated to yield the charge (the differentials weren't exact: there is no Qg(vd, vg, vs) such that Cgd = dQg/dvd, Cgg=dQg/dvg, Cgs=dQg/dvs).

So, it's actually impossible to get a Verilog-A representation of the C-V part of that model.
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liletian
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #2 - Mar 17th, 2010, 8:07am
 
 Hi
 Could you please tell me where I can get it?
 Thank you very much!
 Bests,
Geoffrey_Coram wrote on Mar 17th, 2010, 6:32am:
Silvaco had created such a thing, free for non-commercial use.  I don't know if it's still available.

However, there's a problem with that model (level=3), because the equations are capacitance-based, not charge-based, and the capacitance equations can't be consistently integrated to yield the charge (the differentials weren't exact: there is no Qg(vd, vg, vs) such that Cgd = dQg/dvd, Cgg=dQg/dvg, Cgs=dQg/dvs).

So, it's actually impossible to get a Verilog-A representation of the C-V part of that model.

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marekm
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #3 - Mar 17th, 2010, 8:58am
 
Attached is a version you're welcome to use. We'll post it to the DG modeling web site as well. It will have the capactitance issues Geoffrey points out.

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Marek Mierzwinski
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liletian
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #4 - Mar 17th, 2010, 9:00am
 
thank you very much

marekm wrote on Mar 17th, 2010, 8:58am:
Attached is a version you're welcome to use. We'll post it to the DG modeling web site as well. It will have the capactitance issues Geoffrey points out.


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liletian
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #5 - Mar 17th, 2010, 10:16am
 
Is this the model for VerilogA, when I compile it, It reported tons of errors.

Anyone can help?
thanks
Here is the a small error report\

   "

Error found by spectre during SpectreHDL compile.
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 62: "parameter integer _LEVEL = 3 from [3:3]<<--? ; //Level
       number"
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 62: Error: first range expr(3) must be smaller than second(3)
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 68: "aliasparam NGATE = <<--? TPG;"
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 68: Error: syntax error
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 254: "output_value = max(vnew,vto-.5<<--? );"
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 254: Error: illegal real number.
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 267: "vtemp = vto + .5<<--? ;"
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 267: Error: illegal real number.
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 284: "analog function real spicepnjlim;<<--? "
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 284: Error: can only define a function inside a module
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 285: "input vnew, vold, vt,<<--?  vcrit;"
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 285: Error: syntax error
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 290: "if ((vnew <<--? > vcrit) * (abs(vnew - vold) > (vt + vt)))
       begin"
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 290: Error: undeclared symbol: vnew.
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 290: Error: undeclared symbol: vcrit.
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 290: Error: left operand of type *undef* not supported for
       operator `>'.
   "/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
       line 290: Error: right operand of type *undef* not supported for
       operator `>'.
   Maximum allowable errors exceeded.  Exiting SpectreHDL compilation....





marekm wrote on Mar 17th, 2010, 8:58am:
Attached is a version you're welcome to use. We'll post it to the DG modeling web site as well. It will have the capactitance issues Geoffrey points out.


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patrick
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #6 - Mar 17th, 2010, 10:26am
 
Could it be possible Spectre thinks it's a Spectre HDL file?

Patrick
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liletian
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #7 - Mar 17th, 2010, 11:01am
 
 Hi Patrick
 Then can you suggest on how to fix this problem?
 Thanks
patrick wrote on Mar 17th, 2010, 10:26am:
Could it be possible Spectre thinks it's a Spectre HDL file?

Patrick

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patrick
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #8 - Mar 17th, 2010, 11:54am
 
I'm not sure how you are running Spectre, but a netlist fragment using ahdl_include as below is how you include VA code.

...
ahdl_include "mos3.va"
...

write some such fragment and run Spectre.
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Geoffrey_Coram
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #9 - Mar 18th, 2010, 5:00am
 
marekm wrote on Mar 17th, 2010, 8:58am:
It will have the capactitance issues Geoffrey points out.


How did you do it?  Did you just pick one of the capacitances to integrate, and ignore the fact that the derivative of that charge won't match the other capacitances?
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Marq Kole
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Hmmm. That's
weird...

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Re: MOSFET LEVEL 3 verilogA model help!
Reply #10 - Mar 18th, 2010, 8:12am
 
It could also relate to the particular version of Spectre you are using. You will need to use a version from the Cadence MMSIM stream to be able to run Verilog-A 2.2 compliant code. If you try to run this with the Spectre version provided as part of Cadence IC 5 you will quite likely encounter issues with the number of language constructs supported.

Marq
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patrick
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #11 - Mar 18th, 2010, 8:45am
 
Marq or Geoffrey - maybe one of you guys could run it in Spectre? Only minor tweaks should be required if any. Sample SPICE style netlist below.

--------------
.hdl mos3.va
.options post

.dc vcc -0.1 4.0 0.01 vg -2.0 6 1.0
vg  g 0 0.5 ac 1.0
vcc d 0 1.5 ac 1.0
vs  s 0 0.0

x1 d g s 0 mos3_va tox=3e-8 nsub=1e16 tpg=1
.end
---------------------
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Geoffrey_Coram
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #12 - Mar 18th, 2010, 10:11am
 
Hmm, several bugs:

1) parameter integer _LEVEL = 3 from [3:3]; //Level number
The endpoints are the same, which is illegal per the LRM; you need
parameter integer _LEVEL = 3 from [3:4); //Level number

2) You need "real" in
analog function spicefetlim
(curiously, you have it in spicepnjlim ...)

3) Real numbers need a digit before the decimal (lines 254, 267, 459, ...)
 output_value = max(vnew,vto-.5);


but after fixing those it runs OK.  I'd also suggest adding the exclude in the _TYPE declaration:
parameter integer _TYPE = 1 from [-1:1] exclude 0;

-Geoffrey
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #13 - Mar 18th, 2010, 12:48pm
 
I've updated the code with Geoffrey's changes (thanks for those, Geoffrey!). I should have mentioned that I had started to put various charge models in as well as different limiting schemes.
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Marek Mierzwinski
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Re: MOSFET LEVEL 3 verilogA model help!
Reply #14 - Jun 18th, 2010, 4:46pm
 
That's great,
can you add m (mult, number of devices) parameter to this model?
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Yuval Shay
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