Is this the model for VerilogA, when I compile it, It reported tons of errors.
Anyone can help?
thanks
Here is the a small error report\
"
Error found by spectre during SpectreHDL compile.
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 62: "parameter integer _LEVEL = 3 from [3:3]<<--? ; //Level
number"
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 62: Error: first range expr(3) must be smaller than second(3)
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 68: "aliasparam NGATE = <<--? TPG;"
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 68: Error: syntax error
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 254: "output_value = max(vnew,vto-.5<<--? );"
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 254: Error: illegal real number.
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 267: "vtemp = vto + .5<<--? ;"
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 267: Error: illegal real number.
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 284: "analog function real spicepnjlim;<<--? "
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 284: Error: can only define a function inside a module
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 285: "input vnew, vold, vt,<<--? vcrit;"
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 285: Error: syntax error
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 290: "if ((vnew <<--? > vcrit) * (abs(vnew - vold) > (vt + vt)))
begin"
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 290: Error: undeclared symbol: vnew.
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 290: Error: undeclared symbol: vcrit.
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 290: Error: left operand of type *undef* not supported for
operator `>'.
"/home/liletian/rfdeExamples/VerilogA_Tutorial/5.1.0/VerilogA_Tutorial/mos3/veri
loga/veriloga.va",
line 290: Error: right operand of type *undef* not supported for
operator `>'.
Maximum allowable errors exceeded. Exiting SpectreHDL compilation....
marekm wrote on Mar 17th, 2010, 8:58am:Attached is a version you're welcome to use. We'll post it to the DG modeling web site as well. It will have the capactitance issues Geoffrey points out.