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Simulation of Shunt Capacitor (Read 4673 times)
ic_engr
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Simulation of Shunt Capacitor
Apr 06th, 2010, 12:35pm
 
Hello All,

I am running a simulation for a Filtering capacitor as a shunt device. The capacitor is connected with 4-terminals. On the lower terminals there is inductances.

I ran two simulations. One set-up I added separate GND node on load side on other one I did NOT add a separate GND node on load side.
For both runs the load is 50 Ohms. I am enclosing both the sim result and the schematic.

What I am confused is which is the correct response ?. The OUT2 is the output on node OUT2.  Does it make sense to have GND node on load side, if I am interested in OUT node relative to local ground and NOT the source GROUND. Note that the source can be RF signal from outside world, so I am not sure what should be the ground for that ???

Any feedback is appreciated.

ic_engr
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capacitor_sch.png
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ic_engr
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Re: Simulation of Shunt Capacitor
Reply #1 - Apr 6th, 2010, 12:43pm
 
Here is the simulation result

ic_engr
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rfcooltools.com
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Re: Simulation of Shunt Capacitor
Reply #2 - Apr 16th, 2010, 11:49am
 
In your circuit version 1 the Vout is not going to tell you the power received by the load.  Vout is relative to what you are calling the source ground.  In reality vout should be relative to the loads ground.  Therefore Vout-v(load_ground) is what the load sees as voltage across itself.

One more comment you should use ports with "sp" since the relative levels are already accounted for in s-parameter simulations.  then convert the s-parameter to Y and its done for you.

J
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ic_engr
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Re: Simulation of Shunt Capacitor
Reply #3 - May 3rd, 2010, 12:04pm
 
So is my variant 2 correct then ??.

ic_engr.
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RFICDUDE
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Re: Simulation of Shunt Capacitor
Reply #4 - May 3rd, 2010, 7:46pm
 
I think your question is "Is it correct to have two ground reference nodes if the inductances represent bond wire connections to the capacitor and load."
Is my understanding correct?

If so, then #2 is not correct because you cannot have a ground reference off chip and on chip be the same if bond wire connections (inductive parasitics) separate the two. You are basically shorting out some of the parasitic effects by having ground references in two locations.

The typical convention (although your mileage may vary) is to have one off chip reference with appropriate estimation for the connection parasitic effects (maybe closer to your #1 case?).

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RFICDUDE
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Re: Simulation of Shunt Capacitor
Reply #5 - May 3rd, 2010, 7:48pm
 
Actually your #1 case doesn't necessarily make much sense for integrated parasitics.
Are the inductances supposed to represent bond wire parasitics?
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ic_engr
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Re: Simulation of Shunt Capacitor
Reply #6 - May 25th, 2010, 9:38am
 
The parasitics are modeling pakage parasitics. The Ground on signal is modeling the signal ground. The right hand side ground is modeling the ground to which the shunt capacitor should shunt unwanted signal.

ic_engr
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RFICDUDE
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Re: Simulation of Shunt Capacitor
Reply #7 - Jun 1st, 2010, 3:49am
 
The correctness of the model depends entirely on what connection configuration you are trying to model.


I assume (because I don't know) that the input and output of the filter are connected using bond wires.
Is this correct?
If so, then you need to add the bond wire models for the input and output RF connections as well. It does not make sense to model the ground connections while ignoring the RF connections.

The second configuration (one ground) does not make sense because I cannot think of a reason why you would have a 50 ohm source/termination where the ground connection has to come through two series bond wires to get to the external ground reference.

Is the filter meant to be external rf input - on chip filter - external rf output?

I assume that the configuration is external rf input - on chip filter - external rf output.
Is this correct?

In this case the external ground connections (two ground reference symbols) maybe more correct if the PCB ground inductance between the two package connections does not matter. With a RF filter it may indeed matter.

Schematics are a form of communication, so when you ask a question please make sure the schematic is a clear as possible to avoid confusion.
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