Hi all,


I have just started looking at a 65 nm PDK, and I have the option of two FETs: nmos and RFnmos. Physically, the only difference is that the RFnmos has a guard ring around it, and also the polysilicon trace for the gate connection is extended on both sides of the FET (probably in order to reduce the series gate resistance).

However, I don't really want to use the FET with the polysilicon gate connection on both sides as later on i am going to model the connections to the transistor terminals in an EM simulator and I don't want the addtional connections to pass over the transistor itself (it may reduce the accuracy).

So instead I want to use the "normal" nmos transistor which does not have a guard ring in the layout. So knowing that the RFnmos is physically just an nmos + a guard ring, is this also true for the transistor model? The transistor uses a BSIM4.5 model. So does the RFnmos use an idential BSIM core model plus an additional model for the guard ring, or does the RFnmos include additional modeling to improve the accuracy at RF?

I have tried looking through the model files, but they are absolutely full of equations and parameters, and it isn't easy to compare them. All help is appreciated.


thanks,
Aaron

I see. Thanks.

In order to model the connections to the transistor, I intended to

1) Do the layout with the transistor and pass DRC
2) remove the transistor and extract a gds file
3) simulate the gds file in HFSS or ADS momentum with properly defined ports
4) extract the s2p files and use them in cadence.

I'm worried that if I route metals over the transistor itself, then it isn't correct to simply remove the transistor when I run my EM simulations. Can you possibly advise a way around this problem? I was thinking I may have to try and use an upper metal layer for traces over the transistor, but this will only minimize the unwanted coupling.


thanks,
Aaron

Yes it is a problem to reconcile the connection model if you have to route over the transistor.

I suppose you could try to set up the HFSS simulation in such a way that you can superimpose the interconnect detail that you are trying to model. For instance, the foundry model probably accounts for the individual gate and d/s metal connections from contact to metal 1, but you want to capture the parasitics from all other metals to those metals as well. Maybe one way to do this is to include metal 1 in the HFSS simulation, but make it an ideal conductor such that only the capacitance from other metals to metal1 is modeled in the HFSS simulation. You may have to be creative with port locations such that the parasitics to foundry model are properly arranged (i.e. ports where the terminals on the model physically correspond to the layout).

I think would be opening a pretty big can of worms if you need to go deeper into the foundry MOS model. It can be done (I suppose), but you need a lot of technical support from the foundry. And the foundry will not stand behind anything you do on your own (of course).