In another thread (
http://www.designers-guide.org/Forum/YaBB.pl?num=1101762622 ) it was discussed how a simplistic calculation for VDSAT is VGS-VTH, but this doesn't work even for BSIM3 because of various additional effects.
I have some designers who are interested in VDSAT for an LDMOS device, which has a channel region and a drift region. In some LDMOS models, such as Philips/NXP's MOS20, there is an internal drain node, and two saturation voltages (one for the channel and one for the drift).
Does anyone have a useful definition of VDSAT that's general enough to handle this case? The designers want to be in saturation, such that that output resistance is "high." So, I could imagine, "VDSAT is the voltage at which the output resistance is ____." Is that number a fixed value? Something that depends on L and W? Dependent on the output resistance at Vds=0?
I'd be interested in hearing your thoughts.