Bandgap reference design is to combine Vbe and K*Vt to generate a voltage reference that is insensitive to temperature.  

Vref=Vbe+K*Vt

Is the bandgap vref still insensitive to process and power supply voltage?

The resistor has +/-20% variations and power supply 10%

Just to expand a bit. The bandgap output voltage is (ideally)
V_OUT = U_T*ln(I_BE/I_S) + K*U_T
where U_T is our friend kT/q and K is a gain ~8

K is determined by ratios so it is process independent.
U_T is determined by your favorite God, and he/she doesn't appear to have plans for changing it, so count that as process independent.

I_BE is the current in the relevant PN junction -- it is process dependent. Generally it is limited by the sheet resistance of your process: +/-30% or so, plus the temp co of the resistors. The temp co can increase or decrease the curvature of the temp response.

I_S is the saturation current (reverse bias leakage) and is +/- 30% or so over process if you have a lazy fab. (IMO it is very well controlled, much better than +/-30%, like the Nwell resistor).

So your process dependent part of the equation is U_T*ln(I_BE/I_S) and the variables are tempered by the ln function.

There are other non-ideal effects, like base current drop across the base resistance. These can be strongly process dependent and need to be designed around.

Power supply rejection is just a matter of shielding the pn junction and its current from power supply variations.