The PLL has an analog voltage to frequency converter at the business end of PLL and excluding phase noise the output frequency will be exact if the filtering before this voltage is sufficient enough then the frequency will closely approximate a steady state.  

It will only approximate a steady state condition where the approximation depends on fractional offset/loop bandwidth/KV/Cpcurrent and comparison frequency. As you state if the loop bandwidth is reduced by several orders then the voltage on the varactor will be relatively constant thus the oscillation frequency closer to target.  but the jumping around between two frequencies will only be evident if the fractional frequency is close to the loop filter cutoff.


for a VCO the time varying signal on the varactor will have the following equation
Vout(t)=A*sin(wt+kv*integ(x(t)))
x(t) being the voltage on the varactor.  If x(t) becomes small as is the case when the loop bandwidth is minimal then the VCO aproximates a sine wave carrier with AM or as you put ithopping between to frequencies  (only integral restricted) .
Vout(t)=A*sin(wt+kv*integ(x(t))) ~=A*(1+kv*integ(x(t))*sin(wt))


http://rfcooltools.com

Mayank wrote on Jun 14^th, 2010, 11:06pm:
Strictly speaking, No. But it is very enough constant frequency.

Mayank wrote on Jun 14^th, 2010, 11:06pm:
No, although I don't know what simulator you use as "PSS/Pnoise".
See http://www.designers-guide.org/Forum/YaBB.pl?num=1268969030


The followings are general notes for you.

- Always describe correct tool's name and vendor's name which you use as tool or simulator.
- Don't do multiple posts which are same content.
- Don't request source code or behavioral model without any efforts.
- There are many simulators which have analyses called as PSS, PAC and Pnoise.
- Describe in detail with using correct terminologies.
- Warnigns are different from Errors.
- ADS is not name of simulator.
- There is no tool which name is Cadence.
- Don't use Direct Plot of Cadence ADE blindly without knowing definition.
- All gains in Direct Plot of Cadence ADE are "right", "true" and "practical" voltage gain.
- Don't mix up Simulation with Post Processing. They are completely different phase.
- MATLAB are different from Simulink.
- Learn measurements using actual instruments. Not "EDA Tool Play

The sequence generated by the fractional-N modulator is pseudo-random, meaning that it eventually repeats. Thus, the fractional-N synthesizer does eventually generate a periodic signal, though the period is the length of the pseudo-random sequence, which is very long relative to the duration of one cycle of the output signal.

You do not say why you are interested in knowing whether the output of the fractional-N synthesizer is periodic. If is because you want to run a PSS analysis, then you posted your question to the wrong board. That would be an RF simulation question, and not an RF design question. If that is your question, then the answer is in effect no, because the period is so long relative to the duration of one cycle of the output signal as to make it completely impractical to run PSS with that period.

-Ken

@ rfcooltools & Ken : That explains the reason why people dont do PSS on Fractional PLLs.

@ Ken : Integer PLL has a periodic Steady state of Operation. I wanted to know if the LPF of Fractional PLL filters modulation Noise & provides a clean enough fractional frequency at PLL output. Sorry Boss, made it sound like a simulator query, but that pss question came to my mind just because noOne here runs pss on Fractional PLL. Thought would ask why alongwith.

@ Sheldon : SDM will eventually repeat it's pseudo-random sequence as Ken says, but since that Time Period is much longer than the Time Period of the PLL Operating Frequency, the spurs would be suppressed.

@ everyone : So,
1.   is the Fractional PLL's frequency clean & stable enough for Analog Sampling of a Signal ?
2.  To check the effect of Fractional PLL clock's effect on Sampling, if i use an ideal sampler operating at PLL clock,  What would be the major spurs i would be observing in SNDR plot of Sampled Signal ??

--
Mayank.