lhlbluesky_lhl
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i have designded a circuit as the figure shows, VI is the input signal, when S1 is closed, VI transfers to Va, then to Vb through the buffer, when S2 is closed, the signal transfered to VO. the buffer is as the figure shows also, it is a two stage opamp with miller compensation, the clock period of S2 is 10MHz, the DC gain of the opamp is 86dB, GBW is 72MHz, then, my question is: when CTRL (that is the inverter signal of S2) goes low, the signal Va (Vb, VO also) has a jump of 50mV or so, however, when CTRL is always low (that is, the opamp works all the time), and when S2 is closed (that is, S2 goes high), the jump is very small, less than 0.2mV. why? what is the reason? i want this voltage jump is as small as possible when S2 is closed (that is, CTRL goes low at the same time). how to solve this problem? please help me, thanks all in advance. thanks all.
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