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what sort of ESD specs are industry standard for high-speed links (> 10 Gbps) (Read 6988 times)
vivkr
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what sort of ESD specs are industry standard for high-speed links (> 10 Gbps)
Jul 12th, 2010, 8:40am
 
I would like to know what kind of ESD specs one might expect for most high-speed links, say faster than 10 Gbps? Also, what is the tendency as one goes to higher and higher speeds?

Of interest are machine model (MM), and maybe CDM type of ESD events. What can I expect to see as specs at 10 Gbps? at 40 Gbps?

Thanks,
Vivek
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neoflash
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Re: what sort of ESD specs are industry standard for high-speed links (> 10 Gbps)
Reply #1 - Jul 16th, 2010, 2:10pm
 
HBM 2000
MM 200
CDM 500
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ghatcher
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Re: what sort of ESD specs are industry standard for high-speed links (> 10 Gbps)
Reply #2 - Jul 20th, 2010, 11:41am
 
I would say 2kV HBM, 1kV MM and 500V CDM are way too aggressive for 10G I/O.  Those numbers are better suited for general purpose I/O.  If you try and meet those specs, you'll end up with a grossly over-designed I/O.

The numbers I have seen in the industry for high speed lines are 1kV HBM and CDM 100V.  

Also, MM itself is an outdated test that is no longer relevant.  JEDEC no longer recommends using MM... only HBM and CDM.  I have attached the JEDEC document that contains their guidelines for qualifying a part (JESD47G).
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vivkr
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Re: what sort of ESD specs are industry standard for high-speed links (> 10 Gbps)
Reply #3 - Jul 21st, 2010, 3:02am
 
ghatcher wrote on Jul 20th, 2010, 11:41am:
I would say 2kV HBM, 1kV MM and 500V CDM are way too aggressive for 10G I/O.  Those numbers are better suited for general purpose I/O.  If you try and meet those specs, you'll end up with a grossly over-designed I/O.

The numbers I have seen in the industry for high speed lines are 1kV HBM and CDM 100V.  

Also, MM itself is an outdated test that is no longer relevant.  JEDEC no longer recommends using MM... only HBM and CDM.  I have attached the JEDEC document that contains their guidelines for qualifying a part (JESD47G).


Thanks! that's very useful. Indeed, I would have considered 2 kV HBM etc. are way too aggressive to be applicable to high-speed IO. I will go through the JEDEC doc you sent (thanks), but I wonder why MM would be obsolete. I would have imagined more like HBM being obsolete. MM would be the classic ESD event during wafersort with needle probing, and CDM during packaging.

Regards,
Vivek
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loose-electron
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Re: what sort of ESD specs are industry standard for high-speed links (> 10 Gbps)
Reply #4 - Aug 31st, 2010, 4:33pm
 
vivkr wrote on Jul 21st, 2010, 3:02am:
(thanks), but I wonder why MM would be obsolete. I would have imagined more like HBM being obsolete. MM would be the classic ESD event during wafersort with needle probing, and CDM during packaging.


If you got ESD issues when working with wafers or packaging die, then the system needs fixing, not the ESD protection.

Faster the data rate, the lower the ESD values, purely junction size, vs capacitance vs. data rate.

ESD Protection = a LPF due to all the parasitics.
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vivkr
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Re: what sort of ESD specs are industry standard for high-speed links (> 10 Gbps)
Reply #5 - Sep 2nd, 2010, 7:09am
 
Agree with you fully Jerry. But then, you might just be shipping wafers and your customer may be performing the final dicing and assembly for cost reasons. At any rate, you could always argue that if you are being asked to build in some unreasonable level of ESD protection, then there is something going wrong somewhere higher up in the system. After all, most high-performance chips nowadays have limited direct contact to the external world.

So I would say that one ought to have limited ESD protection for such stuff so that the device characteristics and performance are not adversely affected by exposure to the residual ESD during test and assembly, unless of course the device is intended for use in a particularly harsh environment for some reason.

But you can't tell that to your customer, can you?

Vivek
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Re: what sort of ESD specs are industry standard for high-speed links (> 10 Gbps)
Reply #6 - Sep 2nd, 2010, 8:16pm
 
Wafer carriers are set up to be lightly conductive plastic for this reason. Likewise waffle packs for cut dice.
Any bonding station on the planet is set up for single potential builds.

Most ESD events happen in either crappy board level builds
(sloppy handling without mats-straps-etc) or most common is after its in the board and applications environment.

Limited contact with the outside world? Hmmm.... depends on the application its pretty tough to generalize that one.

vivkr wrote on Sep 2nd, 2010, 7:09am:
Agree with you fully Jerry. But then, you might just be shipping wafers and your customer may be performing the final dicing and assembly for cost reasons. At any rate, you could always argue that if you are being asked to build in some unreasonable level of ESD protection, then there is something going wrong somewhere higher up in the system. After all, most high-performance chips nowadays have limited direct contact to the external world.

So I would say that one ought to have limited ESD protection for such stuff so that the device characteristics and performance are not adversely affected by exposure to the residual ESD during test and assembly, unless of course the device is intended for use in a particularly harsh environment for some reason.

But you can't tell that to your customer, can you?

Vivek

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Jerry Twomey
www.effectiveelectrons.com
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Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
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