Hi,

Hope can have some synthesizer experts to comment on this
question.

Some reference and many recent approaches show that it is getting popular to do phase error correction in fractional synthesizers.

Furthermore,  people are re-quantizing the PEC correction DAC so that there is no need for a very fine DAC.

The re-quantization of the PEC residue inside synthesizer is usually done by a sigma-delta modulator.

As shown in the figure, the requantization modulator is usually working at the same clock rate of the first modulator. As we know, the modulator is usually working on the input which changes much slower than the clock rate. However, in this setup, the 2nd modulator is working on the input signal which changes in significant step every clock cycle, is there any issue with it?  

Hi Neoflash,

Is the accumulator block shown in your figure really a SDM?

Hi Neoflash,

I am not an expert on SDM's but that both the SDM's together in the figure looks similar to a second order SDM with some portions missing. In a second order SDM the error output from the first modulator going to the second one changes at the reference clock frequency. Therefore I would have expected some quantization noise at the output of the second SDM provided that the input is changing at no more than the reference clock (if the input was changing much faster than the reference clock, then the noise might be unshaped).

How did you measure the quantization noise and what input signal did you use for this?

I also re-do the simulation and found that the noise of the 2nd stage is indeed shaped.

I guess something went wrong in my previous setup.

Thanks for your trial.

I realized that although the input of the 2nd stage is changing rapidly, the quantization noise will get the same transfer function. The output noise spectrum will be shaped as long as the quantization itself is still white.

Thanks,
Neo