Hi all,

I am designing a chip with many different channels, and each of which has a separate pipelined ADC.  I'm trying to decide how to partition the clocking for these ADCs.  My choices are:

1.  Use a non-overlapping clock generator for each pipeline, and bus a single master clock around.

2.  Use a non-overlapping clock generator for a group of ADCs (for example for every 4 pipelines).  In this case I'm bussing the clock phases around a bit, but not too much.

3.  Use a single non-overlapping clock generator and bus the different clock phases around.

My initial thought is that (1) makes the most sense.  I don't have an area problem since the chip is in 65nm (the clock generator will be small).  Using scheme (1) will lower the overall load I'm driving, since while I have more clock generators, they will for the most part only drive switches since the total amount of interconnect will be shorter than if I do (2) or (3).  Therefore, since power is proportional to C, I think scheme (1) will be the lowest power of the schemes.

Can anyone see either a. a problem with this thinking, or b. a potential gotcha I haven't thought of?

Thanks,
Carl