Hi guys,

I'm doing a simulation of a 3rd order SD based synthesizer in time domain and its analysis in frequency domain.

Also, I'm using Perrot's PLL assistant software for reference.

The result is not that close between time domain and frequency domain. I will attach them both in the post. I'm using hspice + verilogA for time domain simulation. (Perrot's software for some reason give the same result for 3rd order and 2nd order modulator so the result from his cppsim is not used here. )

I've tried a couple of ways to correlate them but still not close enough. Not sure which result is correct.

The parameter I used:

Kvco = 1e9 Hz/v
Fref  = 156.25e6
Rz    = 5k
CB   = 1n
Cs    = 8pf
N     = 19.125337
Modulator order = 3

Thanks for advice.  


(As shown in the figure, time domain shows much higher noise than frequeny domain)

Hi Neo,

- can you detail how you did the frequency domain simulation?
- in your time domain model, was the VCO the only noise source and were all blocks in VerilogA?
- for the time domain again, for how many cycles (I am guessing fc is around 3GHz) was it run and how did you calculate the phase noise plot?

Why would the small signal ac analysis be close to time domain simulation results? Even for simple baseband signals, there can be considerable difference.

I'll bet that some of the individual blocks (not the VCO) can have differences of several db between small signal analysis and time domain analysis. If you do find out that there is this difference in their transfer functions, please do let me know - I am curious about it.