vp1953 wrote on Sep 18th, 2010, 8:44am:Your phase noise plot (titled USB_phase noise, lower right chart), how did you generate this?
There is no such noise.
It is "USB Noise" not "USB Phase Noise".
See
http://www.designers-guide.org/Forum/YaBB.pl?num=1274422891Also see
http://www.designers-guide.org/Forum/YaBB.pl?num=1280323054Basically same as a link although this Hysteresis Buffer case is driven circuit not autonomous circuit.
vp1953 wrote on Sep 18th, 2010, 8:44am:Just a quick and dirty back of the envelope calculation shows close results - assuming gate thermal noise dominates,
Biggest contributor to output noise is a fricker noise of MN3 not thermal noise.
If size of MN3 is larger and then width of hysteresis is wider, sideband noise from MN3 is larger.
However total fricker noise of MN3 itself is smaller for larger MN3.
See "deriv(out)" in
http://www.designers-guide.org/Forum/Attachments/Hysteresis_2.pngIf a transition is sharper, output noise will be smaller generally.
But it is not true for my Hysteresis Buffer case.
I will survey about this more.
vp1953 wrote on Sep 18th, 2010, 8:44am:As pointed by Mayank, the bias point is varying for the hysteretic circuit does vary
and this alone should indeed produce some variation in the output phase noise,
Such thing is natural and common effect.
Consider "Bias dependent Noise" and then "Cyclostationary Noise".
Effects of periodical varying bias points are surely taken into Slave small signal noise analysis subjected to master large signal steady state analysis.
I think we can never escape fairly large degradation of phase noise if we implement Hysteresis characteristics having meaningful Hysteresis width.
I can see many cases where external TCXO signal is inputed via Hysteresis buffer for reference clock of PLL Synthesizer.
However could it cause very serious degradation of phase noise of PLL Synthesizer ?