Now , DUT has I/O (bi-directional) port w/t pull up or pull down resister.

So, i wana check this function of this I/O.

plz refer to my appended file to show testbench.
-JTAG task(verilog-D)
-LevelShifter( up to I/O voltage )
-DUT

for checking behavior of these I/O , at first i make module on VAMS.

//------------------------------------------
module LS_ams( Ain , A5vout );

input  Ain;
output A5vout;

electrical Ain,A5vout;

real temp;

analog begin
@(cross(V(Ain)-0.7,0));
  if(V(Ain)>0.1) temp = 1;
  else temp=0;

V(A5vout) <+ 5*transition(temp,0,1n,1n);

end

endmodule
//------------------------------------------


about this, so many questions i have...
at first, i want 2 know 2 question as first step.

1) Hiz case
How does connect function works  when JTAG task(verilog-D) drive  Hiz?
Does connect function which tool insert automatically translate Hiz directly ?

now it seems so( trans Hiz ) on my simulation results.
my understanding is correct?

2)  output impedance
how should i care for output impedance of this vams module.

now it seems so low impedance on my simulation.
cos, i can't fond pull up function of I/O.



plz let me know...