Hi,

I am trying to write a compact model for snapback effect in LDMOS. KCL and KVL for  the Equivalent circuit results in a node voltage of the form :
V(n,0) = C1+ C2*exp(V(n,0)/Vt)    ; (C1>>C2)

This has two solutions for V(n,0) . What do i have to do to get the higher value solution? My code in VerilogA always gives me the lower value solution for V(n,0 ) which is close to trivial solution.

Thanks,

Ujwal