Hi Newic,

I dont think it is possible to shield the bottom parasitic coupling cap to substrate. Putting a plain metal structure between the bottom plate and the substrate increases the coupling cap to substrate (since the effective thickness of the cap has come down due to the thickness of the additional metal layer). Psub tap may increase the coupling cap depending on what exactly your psub is.

newic wrote on Oct 16^th, 2010, 8:29am:


Leaving it "blank" usually means metal fill will be under  and around that capacitor anyway unless you draw metal exclusion layers. If using a MiM cap pcell, often they'll include a layer to do this exclusion depending on your pdk. metal fill is needed to planarise the back-end-of-line processing.
if you can exclude fill without violating drc, then shielding the bottom plate with say metal 1 will increase the parasitic capacitance but now to a net of your choice (usually something quiet), and the Q of the parasitic capacitor can be improved, if that matters to you.

Hi ACWWong,

Thank you much for your explanation. I was clearly mistaken about not being able to avoid substrate coupling.

More than getting a higher Q (which can be 50 or higher for MiM caps), in many instances it is important to avoid any parasitics to gnd. For an AC signal, both metal 1 tied to a voltage (as you have stated in your example) and substrate are at virtual gnd. Would this method not increase the effective parasitic to (virtual) gnd?

Clearly there are benefits of using metal 1 tied to a voltage say, to avoid a any coupling of signals via substrate.

I was thinking that if the bottom plate M5 of the mim cap is ground. Could I still fill M1-M2-M3 with ground plate underneath the mim cap (metal density issue)?
The parasitic cap between M5 to Metal-n should not be an issue because they are both ground. Doe it matter?