newic wrote on Oct 16th, 2010, 8:29am:How about the shielding at the bottom side? Shall I shield it with psub tap or just leave it blank?
Leaving it "blank" usually means metal fill will be under and around that capacitor anyway unless you draw metal exclusion layers. If using a MiM cap pcell, often they'll include a layer to do this exclusion depending on your pdk. metal fill is needed to planarise the back-end-of-line processing.
if you can exclude fill without violating drc, then shielding the bottom plate with say metal 1 will increase the parasitic capacitance but now to a net of your choice (usually something quiet), and the Q of the parasitic capacitor can be improved, if that matters to you.