Hello designers,

I understand there was already some discussion of this topic on the forum, but looks like none of them can be comprehensive.  Appreciate that you can put thought over here make this topic beneficial to most of the users

I am simply referring to the dynamic latched comparator (preamp + regenerative latch) in which a clock/strobe signal is used to trigger the regeneration. As I know, accurate INPUT-referred noise simulation for such circuit is always difficult for the designers. The following are the solutions generally adopted by the designers

1) Ignore the noise from regenerative latch, only taking care of the noise of preamp or try to make sure that the noise from latch is negligible. I think this is quite common approach in the old days, but becoming more risky in the designs in which the preamp does not have enough gain, or even there is no preamp.

2) Use transient noise option. This is the one I am currently using, but extremely time-consuming and need more effort on the post-processing on the simulation result. Here are the steps, assuming a input-referred noise with Gaussian distribution
 2.a: determine the comparator offset (systematic only, random mismatch not introduced yet) using a similar method as in http://www.designers-guide.org/Analysis/comparator.pdf and exclude its effect in the simulations afterward.
 2.b: After excluding the effect of offset, impose a small difference on the comparator inputs, with transient noise turning on, run a quite long time transient simulation (>1000 clk cycles). Due to the existence of transience noise, the comparator output can be both HIGH or LOW. The probability of logic HIGH is a function of the noise level. By sweeping the input difference, a cumulative distribution curve can be obtained, as in the example in the attachment (ref: Nuzzo, De Bernardinis, Terreni & Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," TCAS, 2008). Buy curve fitting in Matlab, I can get the standard deviation (σ) of the Gaussian noise distribution.

The advantage of this method is in that similar testbench can be used in the measurement to compare with simulation. But as I mentioned, quite time-consuming (at least 20 swept points, >1000 clk cycles per point), and need post-processing in Matlab.

3) PSS/PNOISE. I am quite familiar with the PSS/PNOISE setup as in the sw-cap filter and VCO circuits. But met significant difficulties in dynamic latched comparator simulation. What I am currently doing is as below
 3.a: Given a clock frequency Fclk, a square-wave comparator input with frequency of Fclk/2 is applied.
 3.b: A toggled comparator output with frequency Fclk/2 can be obtained.
 3.c: By PSS/PNOISE, a output noise/jitter can be obtained, even though I am not quite sure whether it makes sense.
 3.d: Did not find way to read out the input-referred noise yet, as I did not know how to determine the gain of such comparator in Spectre, as it is highly time-varying.

Actually I am not confident with this setup, does anybody think it is possible to get a input-referred noise for the comparator directly? Any suggestion is highly appreciated.

Raymond Yu wrote on Oct 18^th, 2010, 6:19pm:
I don't think so.

Raymond Yu wrote on Oct 18^th, 2010, 6:19pm:
If your interests are quantities averaged over one period, there is no reason why you can't adopt PSS/PAC and PSS/Pnoise(sources).

Conventional AC and Noise analysis at specific time during Transient Analysis are also valuable for your application.
http://www.designers-guide.org/Forum/YaBB.pl?num=1272909056

pancho_hideboo wrote on Oct 19^th, 2010, 7:11am:


Again, I tried to figure out how the gain is defined in such circuit.
I will try this and let you know the outcome, thanks

vp1953 wrote on Oct 21^st, 2010, 6:27pm:


Hi,
The comparator will be used in a swiched-cap SAR ADC, input-referred noise is needed to decide the design constraints for the ADC.
I agree that for some applications in which the BER is the main concern for instance, taking care of noise/jitter at the output is almost good enough.

vp1953 wrote on Oct 21^st, 2010, 6:27pm:


The picture I attached is a little misleading as I failed to show the label of Y-axis. It is actually the probability of output "HIGH"in stead of voltage. Sorry for the inconvenience caused.

I am quite sure that Mr. pancho_hideboo didn't get the whole picture.
The estimation of noise in latched comparator is not a trivial task, and there are just 2 efficient approaches I know. One of them was cited before, and is from Nuzzo et al. The other one is also from TCAS-1, search for "Simulation and Analysis of Random Decision Errors
in Clocked Comparators", by Kim, J. et al. This paper will answer your questions about time-varying gain.

Again, this is not a straightforward procedure, and will take some amount of scripting and post-processing. So, in opposition to what Mr.
pancho said, this topic can be useful to a lot of people that are actually able to understand the problem.

Hi

I am doing exactly the same simulation that Raymond is going.

Transient Noise Method
I apply a dc voltage to the comparator input and clock the comparator many times and calculate the probability of getting '1'. Then I repeat this by sweeping the input and drawing the probability density function. Fitting it to the erf function produces the equivalent input noise.

This method is logical and straightforward.

PNoise method
I apply a sine wave at the one of the comparator inputs and a threshold voltage on the other input. I chose the input frequency to be half the clock frequency so everything is periodic. Then I measure the jitter (Jc) at the zero crossing of the input. I then multiply this jitter by the slope of the signal (which is the frequency) to get the equivalent input noise.



The 2 results do not match and I am not sure which one is the correct one. I was wondering if someone has figured this out and has a reliable method of doing it.

Thanks

Hi Stephan,

Your plot is interesting. I want to know how you plot the spectrum of JitterriseRMS (that curve in red)? Do you run transient noise simulation and do DFT on the jitter result?

Thanks
Yawei

Hi Yawei,

My tran noise based plot is created quite simple:

as I remember, I run the tran noise for e.g. 1000 periods or more.
Then I use the Viva calculator to get the jitter vs periods.
On this I can calculate the standard deviation which is the RMS jitter. So no DFT is done!!

Bye Stephan