the_wavefunction
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Posts: 10
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Hi,
One of my circuits in Cadence needed a high performance pmos current mirror and I decided to simulate it initially using Verilog-A.
Essentially, my idea of the mirror circuit was to implement two simple resistive branches with one being the probe and the other, the source. It was also vital that in addition to the mirrored current, the voltage at the output terminal track the input terminal voltage as well.
However, according to simulations, when the current is mirrored properly, the terminal voltage is not and vice versa. I do realize that in Verilog-A, a branch cannot be both a flow and potential source simultaneously!
So, after numerous revisions the present version of my code looks like this: ----------------------------------------------------------------- `include "constants.vams" `include "disciplines.vams"
module curr_mirr(srcA, srcB, mrrA, mrrB);
input srcA,srcB; // source branch inout mrrA; // mrrA, srcA are tied to Vdd externally output mrrB; // mrrA, mrrB - mirror branch
electrical srcA, srcB, mrrA, mrrB; electrical int; // node joining current source and Rmodel
real Rmodel;
analog begin @(initial_step) begin Rmodel = 10K; end Rmodel = 10K; V(srcA,srcB) <+ I(srcA,srcB) * Rmodel; I(mrrA,int) <+ I(srcA,srcB); V(int,mrrB) <+ I(int,mrrB) * Rmodel;
end
endmodule -----------------------------------------------------------
A simulation of this code tracks the current, but not the terminal voltage. In other words: V(srcB) ≠ V(mrrB), which is against the desired result.
Any suggestions or opinions on this are utmost welcome!
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